Datasheet

www.ti.com USCI Registers: I
2
C Mode
17.4 USCI Registers: I
2
C Mode
The USCI registers applicable in I
2
C mode for USCI_B0 are listed in Table 17-2, and for USCI_B1 in
Table 17-3.
Table 17-2. USCI_B0 Control and Status Registers
Register Short Form Register Type Address Initial State
USCI_B0 control register 0 UCB0CTL0 Read/write 068h 001h with PUC
USCI_B0 control register 1 UCB0CTL1 Read/write 069h 001h with PUC
USCI_B0 bit rate control register 0 UCB0BR0 Read/write 06Ah Reset with PUC
USCI_B0 bit rate control register 1 UCB0BR1 Read/write 06Bh Reset with PUC
USCI_B0 I
2
C interrupt enable register UCB0I2CIE Read/write 06Ch Reset with PUC
USCI_B0 status register UCB0STAT Read/write 06Dh Reset with PUC
USCI_B0 receive buffer register UCB0RXBUF Read 06Eh Reset with PUC
USCI_B0 transmit buffer register UCB0TXBUF Read/write 06Fh Reset with PUC
USCI_B0 I
2
C own address register UCB0I2COA Read/write 0118h Reset with PUC
USCI_B0 I
2
C slave address register UCB0I2CSA Read/write 011Ah Reset with PUC
SFR interrupt enable register 2 IE2 Read/write 001h Reset with PUC
SFR interrupt flag register 2 IFG2 Read/write 003h 00Ah with PUC
NOTE: Modifying SFR bits
To avoid modifying control bits of other modules, it is recommended to set or clear the IEx
and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Table 17-3. USCI_B1 Control and Status Registers
Register Short Form Register Type Address Initial State
USCI_B1 control register 0 UCB1CTL0 Read/write 0D8h Reset with PUC
USCI_B1 control register 1 UCB1CTL1 Read/write 0D9h 001h with PUC
USCI_B1 baud rate control register 0 UCB1BR0 Read/write 0DAh Reset with PUC
USCI_B1 baud rate control register 1 UCB1BR1 Read/write 0DBh Reset with PUC
USCI_B1 I
2
C interrupt enable register UCB1I2CIE Read/write 0DCh Reset with PUC
USCI_B1 status register UCB1STAT Read/write 0DDh Reset with PUC
USCI_B1 receive buffer register UCB1RXBUF Read 0DEh Reset with PUC
USCI_B1 transmit buffer register UCB1TXBUF Read/write 0DFh Reset with PUC
USCI_B1 I
2
C own address register UCB1I2COA Read/write 017Ch Reset with PUC
USCI_B1 I
2
C slave address register UCB1I2CSA Read/write 017Eh Reset with PUC
USCI_A1/B1 interrupt enable register UC1IE Read/write 006h Reset with PUC
USCI_A1/B1 interrupt flag register UC1IFG Read/write 007h 00Ah with PUC
467
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
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