Datasheet

www.ti.com USCI Operation: I
2
C Mode
17.3.6 Using the USCI Module in I
2
C Mode with Low-Power Modes
The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When
SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI
module automatically activates it when needed, regardless of the control-bit settings for the clock source.
The clock remains active until the USCI module returns to its idle condition. After the USCI module returns
to the idle condition, control of the clock source reverts to the settings of its control bits. Automatic clock
activation is not provided for ACLK.
When the USCI module activates an inactive clock source, the clock source becomes active for the whole
device and any peripheral configured to use the clock source may be affected. For example, a timer using
SMCLK will increment while the USCI module forces SMCLK active.
In I
2
C slave mode no internal clock source is required because the clock is provided by the external
master. It is possible to operate the USCI in I
2
C slave mode while the device is in LPM4 and all internal
clock sources are disabled. The receive or transmit interrupts can wake up the CPU from any low power
mode.
17.3.7 USCI Interrupts in I
2
C Mode
There are two interrupt vectors for the USCI module in I
2
C mode. One interrupt vector is associated with
the transmit and receive interrupt flags. The other interrupt vector is associated with the four state change
interrupt flags. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the
GIE bit is set, the interrupt flag will generate an interrupt request. DMA transfers are controlled by the
UCBxTXIFG and UCBxRXIFG flags on devices with a DMA controller.
17.3.7.1 I
2
C Transmit Interrupt Operation
The UCBxTXIFG interrupt flag is set by the transmitter to indicate that UCBxTXBUF is ready to accept
another character. An interrupt request is generated if UCBxTXIE and GIE are also set. UCBxTXIFG is
automatically reset if a character is written to UCBxTXBUF or if a NACK is received. UCBxTXIFG is set
when UCSWRST = 1 and the I
2
C mode is selected. UCBxTXIE is reset after a PUC or when
UCSWRST = 1.
17.3.7.2 I
2
C Receive Interrupt Operation
The UCBxRXIFG interrupt flag is set when a character is received and loaded into UCBxRXBUF. An
interrupt request is generated if UCBxRXIE and GIE are also set. UCBxRXIFG and UCBxRXIE are reset
after a PUC signal or when UCSWRST = 1. UCxRXIFG is automatically reset when UCxRXBUF is read.
17.3.7.3 I
2
C State Change Interrupt Operation
Table 17-1 describes the I
2
C state change interrupt flags.
Table 17-1. State Change Interrupt Flags
Interrupt Flag Interrupt Condition
Arbitration-lost. Arbitration can be lost when two or more transmitters start a transmission simultaneously, or
when the USCI operates as master but is addressed as a slave by another master in the system. The
UCALIFG
UCALIFG flag is set when arbitration is lost. When UCALIFG is set the UCMST bit is cleared and the I
2
C
controller becomes a slave.
Not-acknowledge interrupt. This flag is set when an acknowledge is expected but is not received.
UCNACKIFG
UCNACKIFG is automatically cleared when a START condition is received.
Start condition detected interrupt. This flag is set when the I
2
C module detects a START condition together
UCSTTIFG with its own address while in slave mode. UCSTTIFG is used in slave mode only and is automatically
cleared when a STOP condition is received.
Stop condition detected interrupt. This flag is set when the I
2
C module detects a STOP condition while in
UCSTPIFG slave mode. UCSTPIFG is used in slave mode only and is automatically cleared when a START condition is
received.
465
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
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