Datasheet

Wait
State
Start HIGH
Period
SCL From
Device 1
SCL From
Device 2
Bus Line
SCL
LOW,MIN HIGH,MIN
BRCLK
(UCBRx – 1) / 2
t = t =
f
LOW,MIN HIGH,MIN
BRCLK
UCBRx / 2
t = t =
f
BRCLK
BitClock
f
f =
UCBRx
USCI Operation: I
2
C Mode www.ti.com
17.3.5 I
2
C Clock Generation and Synchronization
The I
2
C clock SCL is provided by the master on the I
2
C bus. When the USCI is in master mode, BITCLK is
provided by the USCI bit clock generator and the clock source is selected with the UCSSELx bits. In slave
mode the bit clock generator is not used and the UCSSELx bits are don’t care.
The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division factor of the USCI clock
source, BRCLK. The maximum bit clock that can be used in single master mode is f
BRCLK
/4. In multi-master
mode the maximum bit clock is f
BRCLK
/8. The BITCLK frequency is given by:
The minimum high and low periods of the generated SCL are
when UCBRx is even and
when UCBRx is odd.
The USCI clock source frequency and the prescaler setting UCBRx must to be chosen such that the
minimum low and high period times of the I
2
C specification are met.
During the arbitration procedure the clocks from the different masters must be synchronized. A device that
first generates a low period on SCL overrules the other devices forcing them to start their own low periods.
SCL is then held low by the device with the longest low period. The other devices must wait for SCL to be
released before starting their high periods. Figure 17-16 shows the clock synchronization. This allows a
slow slave to slow down a fast master.
Figure 17-16. Synchronization of Two I
2
C Clock Generators During Arbitration
17.3.5.1 Clock Stretching
The USCI module supports clock stretching and also makes use of this feature as described in the
operation mode sections.
The UCSCLLOW bit can be used to observe if another device pulls SCL low while the USCI module
already released SCL due to the following conditions:
• USCI is acting as master and a connected slave drives SCL low.
• USCI is acting as master and another master drives SCL low during arbitration.
The UCSCLLOW bit is also active if the USCI holds SCL low because it is waiting as transmitter for data
being written into UCBxTXBUF or as receiver for the data being read from UCBxRXBUF.
The UCSCLLOW bit might get set for a short time with each rising SCL edge because the logic observes
the external SCL and compares it to the internally generated SCL.
464
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
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