Datasheet

www.ti.com USCI Operation: I
2
C Mode
17.3.4.2 Master Mode
The USCI module is configured as an I
2
C master by selecting the I
2
C mode with UCMODEx = 11 and
UCSYNC = 1 and setting the UCMST bit. When the master is part of a multi-master system, UCMM must
be set and its own address must be programmed into the UCBxI2COA register. When UCA10 = 0, 7-bit
addressing is selected. When UCA10 = 1, 10-bit addressing is selected. The UCGCEN bit selects if the
USCI module responds to a general call.
17.3.4.2.1 I
2
C Master Transmitter Mode
After initialization, master transmitter mode is initiated by writing the desired slave address to the
UCBxI2CSA register, selecting the size of the slave address with the UCSLA10 bit, setting UCTR for
transmitter mode, and setting UCTXSTT to generate a START condition.
The USCI module checks if the bus is available, generates the START condition, and transmits the slave
address. The UCBxTXIFG bit is set when the START condition is generated and the first data to be
transmitted can be written into UCBxTXBUF. As soon as the slave acknowledges the address the
UCTXSTT bit is cleared.
The data written into UCBxTXBUF is transmitted if arbitration is not lost during transmission of the slave
address. UCBxTXIFG is set again as soon as the data is transferred from the buffer into the shift register.
If there is no data loaded to UCBxTXBUF before the acknowledge cycle, the bus is held during the
acknowledge cycle with SCL low until data is written into UCBxTXBUF. Data is transmitted or the bus is
held as long as the UCTXSTP bit or UCTXSTT bit is not set.
Setting UCTXSTP will generate a STOP condition after the next acknowledge from the slave. If UCTXSTP
is set during the transmission of the slave’s address or while the USCI module waits for data to be written
into UCBxTXBUF, a STOP condition is generated even if no data was transmitted to the slave. When
transmitting a single byte of data, the UCTXSTP bit must be set while the byte is being transmitted, or
anytime after transmission begins, without writing new data into UCBxTXBUF. Otherwise, only the
address will be transmitted. When the data is transferred from the buffer to the shift register, UCBxTXIFG
will become set indicating data transmission has begun and the UCTXSTP bit may be set.
Setting UCTXSTT will generate a repeated START condition. In this case, UCTR may be set or cleared to
configure transmitter or receiver, and a different slave address may be written into UCBxI2CSA if desired.
If the slave does not acknowledge the transmitted data the not-acknowledge interrupt flag UCNACKIFG is
set. The master must react with either a STOP condition or a repeated START condition. If data was
already written into UCBxTXBUF it will be discarded. If this data should be transmitted after a repeated
START it must be written into UCBxTXBUF again. Any set UCTXSTT is discarded, too. To trigger a
repeated start UCTXSTT needs to be set again.
Figure 17-12 shows the I
2
C master transmitter operation.
459
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
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