Datasheet

S SLA/R
A DATA
A P
UCTR=1 (Transmitter)
UCSTTIFG=1
UCBxTXIFG=1
UCSTPIFG=?0
UCBxTXBUF discarded
Reception of own
address and
transmission of data
bytes
Bus stalled (SCL held low)
until data available
DATADATA
A
UCSTPIFG=1
UCSTTIFG=0
A
A
DATA
A S SLA/R
UCTR=1 (Transmitter)
UCSTTIFG=1
UCBxTXIFG=1
UCBxTXBUF discarded
DATA
A S SLA/W
UCTR=0 (Receiver)
UCSTTIFG=1
Arbitration lost as
master and
addressed as slave
UCALIFG=1
UCMST=0
UCTR=1 (Transmitter)
UCSTTIFG=1
UCBxTXIFG=1
UCSTPIFG=0
UCBxTXIFG=0
Repeated start
continue as
slave transmitter
Repeated start
continue as
slave receiver
Write data to UCBxTXBUF
UCBxTXIFG=1
UCBxTXIFG=0
UCBxTXIFG=0
Write data to UCBxTXBUF
www.ti.com
USCI Operation: I
2
C Mode
17.3.4.1.1 I
2
C Slave Transmitter Mode
Slave transmitter mode is entered when the slave address transmitted by the master is identical to its own
address with a set R/W bit. The slave transmitter shifts the serial data out on SDA with the clock pulses
that are generated by the master device. The slave device does not generate the clock, but it will hold
SCL low while intervention of the CPU is required after a byte has been transmitted.
If the master requests data from the slave the USCI module is automatically configured as a transmitter
and UCTR and UCBxTXIFG become set. The SCL line is held low until the first data to be sent is written
into the transmit buffer UCBxTXBUF. Then the address is acknowledged, the UCSTTIFG flag is cleared,
and the data is transmitted. As soon as the data is transferred into the shift register the UCBxTXIFG is set
again. After the data is acknowledged by the master the next data byte written into UCBxTXBUF is
transmitted or if the buffer is empty the bus is stalled during the acknowledge cycle by holding SCL low
until new data is written into UCBxTXBUF. If the master sends a NACK succeeded by a STOP condition
the UCSTPIFG flag is set. If the NACK is succeeded by a repeated START condition the USCI I
2
C state
machine returns to its address-reception state.
Figure 17-9 shows the slave transmitter operation.
Figure 17-9. I
2
C Slave Transmitter Mode
455
SLAU144JDecember 2004Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated