Datasheet

S
1
Slave Address 1st byte
7
Slave Address 2nd byteACKR/W
11
8
ACK
1
Data
8
ACK
1
P
1
1 1 1 1 0 X X
S Slave Address R/W ACK Data ACK Data ACK P
7 8 8
1 1 1 1 1 1
Data Line
Stable Data
Change of Data Allowed
SDA
SCL
www.ti.com USCI Operation: I
2
C Mode
START and STOP conditions are generated by the master and are shown in Figure 17-3. A START
condition is a high-to-low transition on the SDA line while SCL is high. A STOP condition is a low-to-high
transition on the SDA line while SCL is high. The bus busy bit, UCBBUSY, is set after a START and
cleared after a STOP.
Data on SDA must be stable during the high period of SCL as shown in Figure 17-4. The high and low
state of SDA can only change when SCL is low, otherwise START or STOP conditions will be generated.
Figure 17-4. Bit Transfer on the I
2
C Bus
17.3.3 I
2
C Addressing Modes
The I
2
C mode supports 7-bit and 10-bit addressing modes.
17.3.3.1 7-Bit Addressing
In the 7-bit addressing format, shown in Figure 17-5, the first byte is the 7-bit slave address and the R/W
bit. The ACK bit is sent from the receiver after each byte.
Figure 17-5. I
2
C Module 7-Bit Addressing Format
17.3.3.2 10-Bit Addressing
In the 10-bit addressing format, shown in Figure 17-6, the first byte is made up of 11110b plus the two
MSBs of the 10-bit slave address and the R/W bit. The ACK bit is sent from the receiver after each byte.
The next byte is the remaining 8 bits of the 10-bit slave address, followed by the ACK bit and the 8-bit
data.
Figure 17-6. I
2
C Module 10-Bit Addressing Format
17.3.3.3 Repeated Start Conditions
The direction of data flow on SDA can be changed by the master, without first stopping a transfer, by
issuing a repeated START condition. This is called a RESTART. After a RESTART is issued, the slave
address is again sent out with the new data direction specified by the R/W bit. The RESTART condition is
shown in Figure 17-7.
453
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
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