Datasheet

USCI Registers: SPI Mode www.ti.com
16.4.10 UC1IE, USCI_A1/USCI_B1 Interrupt Enable Register
7 6 5 4 3 2 1 0
Unused UCB1TXIE UCB1RXIE UCA1TXIE UCA1RXIE
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
Unused Bits 7-4 Unused
UCB1TXIE Bit 3 USCI_B1 transmit interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCB1RXIE Bit 2 USCI_B1 receive interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCA1TXIE Bit 1 USCI_A1 transmit interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCA1RXIE Bit 0 USCI_A1 receive interrupt enable
0 Interrupt disabled
1 Interrupt enabled
16.4.11 UC1IFG, USCI_A1/USCI_B1 Interrupt Flag Register
7 6 5 4 3 2 1 0
Unused UCB1TXIFG UCB1RXIFG UCA1TXIFG UCA1RXIFG
rw-0 rw-0 rw-0 rw-0 rw-1 rw-0 rw-1 rw-0
Unused Bits 7-4 Unused
UCB1TXIFG Bit 3 USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is empty.
0 No interrupt pending
1 Interrupt pending
UCB1RXIFG Bit 2 USCI_B1 receive interrupt flag. UCB1RXIFG is set when UCB1RXBUF has received a complete character.
0 No interrupt pending
1 Interrupt pending
UCA1TXIFG Bit 1 USCI_A1 transmit interrupt flag. UCA1TXIFG is set when UCA1TXBUF empty.
0 No interrupt pending
1 Interrupt pending
UCA1RXIFG Bit 0 USCI_A1 receive interrupt flag. UCA1RXIFG is set when UCA1RXBUF has received a complete character.
0 No interrupt pending
1 Interrupt pending
448
Universal Serial Communication Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
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