Datasheet

www.ti.com USCI Registers: SPI Mode
16.4.7 UCAxTXBUF, USCI_Ax Transmit Buffer Register,
UCBxTXBUF, USCI_Bx Transmit Buffer Register
7 6 5 4 3 2 1 0
UCTXBUFx
rw rw rw rw rw rw rw rw
UCTXBUFx Bits 7-0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift
register and transmitted. Writing to the transmit data buffer clears UCxTXIFG. The MSB of UCxTXBUF is not
used for 7-bit data and is reset.
16.4.8 IE2, Interrupt Enable Register 2
7 6 5 4 3 2 1 0
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw-0 rw-0 rw-0 rw-0
Bits 7-4 These bits may be used by other modules (see the device-specific data sheet).
UCB0TXIE Bit 3 USCI_B0 transmit interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCB0RXIE Bit 2 USCI_B0 receive interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCA0TXIE Bit 1 USCI_A0 transmit interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCA0RXIE Bit 0 USCI_A0 receive interrupt enable
0 Interrupt disabled
1 Interrupt enabled
16.4.9 IFG2, Interrupt Flag Register 2
7 6 5 4 3 2 1 0
UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw-1 rw-0 rw-1 rw-0
Bits 7-4 These bits may be used by other modules (see the device-specific data sheet).
UCB0TXIFG Bit 3 USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is empty.
0 No interrupt pending
1 Interrupt pending
UCB0RXIFG Bit 2 USCI_B0 receive interrupt flag. UCB0RXIFG is set when UCB0RXBUF has received a complete character.
0 No interrupt pending
1 Interrupt pending
UCA0TXIFG Bit 1 USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF empty.
0 No interrupt pending
1 Interrupt pending
UCA0RXIFG Bit 0 USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character.
0 No interrupt pending
1 Interrupt pending
447
SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, SPI Mode
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