Datasheet
USCI Registers: SPI Mode
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16.4.3 UCAxBR0, USCI_Ax Bit Rate Control Register 0,
UCBxBR0, USCI_Bx Bit Rate Control Register 0
7 6 5 4 3 2 1 0
UCBRx - low byte
rw rw rw rw rw rw rw rw
16.4.4 UCAxBR1, USCI_Ax Bit Rate Control Register 1,
UCBxBR1, USCI_Bx Bit Rate Control Register 1
7 6 5 4 3 2 1 0
UCBRx - high byte
rw rw rw rw rw rw rw rw
UCBRx Bit clock prescaler setting. The 16-bit value of (UCxxBR0 + UCxxBR1 × 256) forms the prescaler value.
16.4.5 UCAxSTAT, USCI_Ax Status Register,
UCBxSTAT, USCI_Bx Status Register
7 6 5 4 3 2 1 0
UCLISTEN UCFE UCOE Unused UCBUSY
rw-0 rw-0 rw-0 rw-0
(1)
rw-0 rw-0 rw-0 r-0
r0
(2)
UCLISTEN Bit 7 Listen enable. The UCLISTEN bit selects loopback mode.
0 Disabled
1 Enabled. The transmitter output is internally fed back to the receiver.
UCFE Bit 6 Framing error flag. This bit indicates a bus conflict in 4-wire master mode. UCFE is not used in 3-wire
master or any slave mode.
0 No error
1 Bus conflict occurred
UCOE Bit 5 Overrun error flag. This bit is set when a character is transferred into UCxRXBUF before the previous
character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by
software. Otherwise, it will not function correctly.
0 No error
1 Overrun error occurred
Unused Bits 4-1 Unused
UCBUSY Bit 0 USCI busy. This bit indicates if a transmit or receive operation is in progress.
0 USCI inactive
1 USCI transmitting or receiving
(1)
UCAxSTAT (USCI_Ax)
(2)
UCBxSTAT (USCI_Bx)
16.4.6 UCAxRXBUF, USCI_Ax Receive Buffer Register,
UCBxRXBUF, USCI_Bx Receive Buffer Register
7 6 5 4 3 2 1 0
UCRXBUFx
r r r r r r r r
UCRXBUFx Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shift
register. Reading UCxRXBUF resets the receive-error bits, and UCxRXIFG. In 7-bit data mode, UCxRXBUF
is LSB justified and the MSB is always reset.
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Universal Serial Communication Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
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