Datasheet

www.ti.com USCI Registers: SPI Mode
16.4.1 UCAxCTL0, USCI_Ax Control Register 0,
UCBxCTL0, USCI_Bx Control Register 0
7 6 5 4 3 2 1 0
UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCSYNC=1
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
UCCKPH Bit 7 Clock phase select.
0 Data is changed on the first UCLK edge and captured on the following edge.
1 Data is captured on the first UCLK edge and changed on the following edge.
UCCKPL Bit 6 Clock polarity select.
0 The inactive state is low.
1 The inactive state is high.
UCMSB Bit 5 MSB first select. Controls the direction of the receive and transmit shift register.
0 LSB first
1 MSB first
UC7BIT Bit 4 Character length. Selects 7-bit or 8-bit character length.
0 8-bit data
1 7-bit data
UCMST Bit 3 Master mode select
0 Slave mode
1 Master mode
UCMODEx Bits 2-1 USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1.
00 3-pin SPI
01 4-pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
10 4-pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
11 I
2
C mode
UCSYNC Bit 0 Synchronous mode enable
0 Asynchronous mode
1 Synchronous mode
16.4.2 UCAxCTL1, USCI_Ax Control Register 1,
UCBxCTL1, USCI_Bx Control Register 1
7 6 5 4 3 2 1 0
UCSSELx Unused UCSWRST
rw-0 rw-0 rw-0
(1)
rw-0 rw-0 rw-0 rw-0 rw-1
r0
(2)
UCSSELx Bits 7-6 USCI clock source select. These bits select the BRCLK source clock in master mode. UCxCLK is always
used in slave mode.
00 NA
01 ACLK
10 SMCLK
11 SMCLK
Unused Bits 5-1 Unused
UCSWRST Bit 0 Software reset enable
0 Disabled. USCI reset released for operation.
1 Enabled. USCI logic held in reset state.
(1)
UCAxCTL1 (USCI_Ax)
(2)
UCBxCTL1 (USCI_Bx)
445
SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, SPI Mode
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