Datasheet

USCI Registers: SPI Mode www.ti.com
16.4 USCI Registers: SPI Mode
The USCI registers applicable in SPI mode for USCI_A0 and USCI_B0 are listed in Table 16-2. Registers
applicable in SPI mode for USCI_A1 and USCI_B1 are listed in Table 16-3.
Table 16-2. USCI_A0 and USCI_B0 Control and Status Registers
Register Short Form Register Type Address Initial State
USCI_A0 control register 0 UCA0CTL0 Read/write 060h Reset with PUC
USCI_A0 control register 1 UCA0CTL1 Read/write 061h 001h with PUC
USCI_A0 baud rate control register 0 UCA0BR0 Read/write 062h Reset with PUC
USCI_A0 baud rate control register 1 UCA0BR1 Read/write 063h Reset with PUC
USCI_A0 modulation control register UCA0MCTL Read/write 064h Reset with PUC
USCI_A0 status register UCA0STAT Read/write 065h Reset with PUC
USCI_A0 receive buffer register UCA0RXBUF Read 066h Reset with PUC
USCI_A0 transmit buffer register UCA0TXBUF Read/write 067h Reset with PUC
USCI_B0 control register 0 UCB0CTL0 Read/write 068h 001h with PUC
USCI_B0 control register 1 UCB0CTL1 Read/write 069h 001h with PUC
USCI_B0 bit rate control register 0 UCB0BR0 Read/write 06Ah Reset with PUC
USCI_B0 bit rate control register 1 UCB0BR1 Read/write 06Bh Reset with PUC
USCI_B0 status register UCB0STAT Read/write 06Dh Reset with PUC
USCI_B0 receive buffer register UCB0RXBUF Read 06Eh Reset with PUC
USCI_B0 transmit buffer register UCB0TXBUF Read/write 06Fh Reset with PUC
SFR interrupt enable register 2 IE2 Read/write 001h Reset with PUC
SFR interrupt flag register 2 IFG2 Read/write 003h 00Ah with PUC
NOTE: Modifying SFR bits
To avoid modifying control bits of other modules, it is recommended to set or clear the IEx
and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Table 16-3. USCI_A1 and USCI_B1 Control and Status Registers
Register Short Form Register Type Address Initial State
USCI_A1 control register 0 UCA1CTL0 Read/write 0D0h Reset with PUC
USCI_A1 control register 1 UCA1CTL1 Read/write 0D1h 001h with PUC
USCI_A1 baud rate control register 0 UCA1BR0 Read/write 0D2h Reset with PUC
USCI_A1 baud rate control register 1 UCA1BR1 Read/write 0D3h Reset with PUC
USCI_A1 modulation control register UCA10MCTL Read/write 0D4h Reset with PUC
USCI_A1 status register UCA1STAT Read/write 0D5h Reset with PUC
USCI_A1 receive buffer register UCA1RXBUF Read 0D6h Reset with PUC
USCI_A1 transmit buffer register UCA1TXBUF Read/write 0D7h Reset with PUC
USCI_B1 control register 0 UCB1CTL0 Read/write 0D8h 001h with PUC
USCI_B1 control register 1 UCB1CTL1 Read/write 0D9h 001h with PUC
USCI_B1 bit rate control register 0 UCB1BR0 Read/write 0DAh Reset with PUC
USCI_B1 bit rate control register 1 UCB1BR1 Read/write 0DBh Reset with PUC
USCI_B1 status register UCB1STAT Read/write 0DDh Reset with PUC
USCI_B1 receive buffer register UCB1RXBUF Read 0DEh Reset with PUC
USCI_B1 transmit buffer register UCB1TXBUF Read/write 0DFh Reset with PUC
USCI_A1/B1 interrupt enable register UC1IE Read/write 006h Reset with PUC
USCI_A1/B1 interrupt flag register UC1IFG Read/write 007h 00Ah with PUC
444
Universal Serial Communication Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
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