Datasheet

BRCLK

BitClock

f =

UCBRx

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USCI Operation: SPI Mode

16.3.5 SPI Enable

When the USCI module is enabled by clearing the UCSWRST bit it is ready to receive and transmit. In

master mode the bit clock generator is ready, but is not clocked nor producing any clocks. In slave mode

the bit clock generator is disabled and the clock is provided by the master.

A transmit or receive operation is indicated by UCBUSY = 1.

A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated.

16.3.5.1 Transmit Enable

In master mode, writing to UCxTXBUF activates the bit clock generator and the data will begin to transmit.

In slave mode, transmission begins when a master provides a clock and, in 4-pin mode, when the

UCxSTE is in the slave-active state.

16.3.5.2 Receive Enable

The SPI receives data when a transmission is active. Receive and transmit operations operate

concurrently.

16.3.6 Serial Clock Control

UCxCLK is provided by the master on the SPI bus. When UCMST = 1, the bit clock is provided by the

USCI bit clock generator on the UCxCLK pin. The clock used to generate the bit clock is selected with the

UCSSELx bits. When UCMST = 0, the USCI clock is provided on the UCxCLK pin by the master, the bit

clock generator is not used, and the UCSSELx bits are don’t care. The SPI receiver and transmitter

operate in parallel and use the same clock source for data transfer.

The 16-bit value of UCBRx in the bit rate control registers UCxxBR1 and UCxxBR0 is the division factor of

the USCI clock source, BRCLK. The maximum bit clock that can be generated in master mode is BRCLK.

Modulation is not used in SPI mode and UCAxMCTL should be cleared when using SPI mode for

USCI_A. The UCAxCLK/UCBxCLK frequency is given by:

441

SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, SPI Mode

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