Datasheet

Receive Buffer
UCxRXBUF
Receive Shift Register
Transmit Buffer
UCxTXBUF
Transmit Shift Register
SPI Receive Buffer
Data Shift Register DSR
UCx
SOMI
SOMI
UCxSIMOSIMO
MASTER SLAVE
Px.x UCxSTE
STE
SS
Port.x
UCxCLK
SCLK
MSP430 USCICOMMON SPI
USCI Operation: SPI Mode www.ti.com
16.3.3.1 Four-Pin SPI Master Mode
In 4-pin master mode, UCxSTE is used to prevent conflicts with another master and controls the master
as described in Table 16-1. When UCxSTE is in the master-inactive state:
• UCxSIMO and UCxCLK are set to inputs and no longer drive the bus
• The error bit UCFE is set indicating a communication integrity violation to be handled by the user.
• The internal state machines are reset and the shift operation is aborted.
If data is written into UCxTXBUF while the master is held inactive by UCxSTE, it will be transmitted as
soon as UCxSTE transitions to the master-active state. If an active transfer is aborted by UCxSTE
transitioning to the master-inactive state, the data must be re-written into UCxTXBUF to be transferred
when UCxSTE transitions back to the master-active state. The UCxSTE input signal is not used in 3-pin
master mode.
16.3.4 Slave Mode
Figure 16-3 shows the USCI as a slave in both 3-pin and 4-pin configurations. UCxCLK is used as the
input for the SPI clock and must be supplied by the external master. The data-transfer rate is determined
by this clock and not by the internal bit clock generator. Data written to UCxTXBUF and moved to the TX
shift register before the start of UCxCLK is transmitted on UCxSOMI. Data on UCxSIMO is shifted into the
receive shift register on the opposite edge of UCxCLK and moved to UCxRXBUF when the set number of
bits are received. When data is moved from the RX shift register to UCxRXBUF, the UCxRXIFG interrupt
flag is set, indicating that data has been received. The overrun error bit, UCOE, is set when the previously
received data is not read from UCxRXBUF before new data is moved to UCxRXBUF.
Figure 16-3. USCI Slave and External Master
16.3.4.1 Four-Pin SPI Slave Mode
In 4-pin slave mode, UCxSTE is used by the slave to enable the transmit and receive operations and is
provided by the SPI master. When UCxSTE is in the slave-active state, the slave operates normally.
When UCxSTE is in the slave- inactive state:
• Any receive operation in progress on UCxSIMO is halted
• UCxSOMI is set to the input direction
• The shift operation is halted until the UCxSTE line transitions into the slave transmit active state.
The UCxSTE input signal is not used in 3-pin slave mode.
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Universal Serial Communication Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
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