Datasheet

015
MDB − Memory Data Bus Memory Address Bus − MAB
16
Zero, Z
Carry, C
Overflow, V
Negative, N
16−bit ALU
dst src
R8 General Purpose
R9 General Purpose
R10 General Purpose
R11 General Purpose
R12 General Purpose
R13 General Purpose
R14 General Purpose
R15 General Purpose
R4 General Purpose
R5 General Purpose
R6 General Purpose
R7 General Purpose
R3/CG2 Constant Generator
R2/SR/CG1 Status
R1/SP Stack Pointer
R0/PC Program Counter 0
0
16
MCLK
CPU Registers www.ti.com
Figure 3-1. CPU Block Diagram
3.2 CPU Registers
The CPU incorporates sixteen 16-bit registers. R0, R1, R2, and R3 have dedicated functions. R4 to R15
are working registers for general use.
3.2.1 Program Counter (PC)
The 16-bit program counter (PC/R0) points to the next instruction to be executed. Each instruction uses an
even number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in
the 64-KB address space are performed on word boundaries, and the PC is aligned to even addresses.
Figure 3-2 shows the program counter.
Figure 3-2. Program Counter
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Program Counter Bits 15 to 1 0
44
CPU SLAU144J–December 2004–Revised July 2013
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