Datasheet
Receive Buffer
UCxRXBUF
Receive Shift Register
Transmit Buffer
UCxTXBUF
Transmit Shift Register
SPI Receive Buffer
Data Shift Register (DSR)
UCx
SOMI
SOMI
UCxSIMO SIMO
MASTER SLAVE
Px.x STE
UCxSTE
SS
Port.x
UCxCLK
SCLK
MSP430 USCI COMMON SPI
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USCI Operation: SPI Mode
16.3.2 Character Format
The USCI module in SPI mode supports 7-bit and 8-bit character lengths selected by the UC7BIT bit. In 7-
bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. The UCMSB bit controls the
direction of the transfer and selects LSB or MSB first.
NOTE: Default Character Format
The default SPI character transmission is LSB first. For communication with other SPI
interfaces it MSB-first mode may be required.
NOTE: Character Format for Figures
Figures throughout this chapter use MSB first format.
16.3.3 Master Mode
Figure 16-2 shows the USCI as a master in both 3-pin and 4-pin configurations. The USCI initiates data
transfer when data is moved to the transmit data buffer UCxTXBUF. The UCxTXBUF data is moved to the
TX shift register when the TX shift register is empty, initiating data transfer on UCxSIMO starting with
either the most-significant or least-significant bit depending on the UCMSB setting. Data on UCxSOMI is
shifted into the receive shift register on the opposite clock edge. When the character is received, the
receive data is moved from the RX shift register to the received data buffer UCxRXBUF and the receive
interrupt flag, UCxRXIFG, is set, indicating the RX/TX operation is complete.
Figure 16-2. USCI Master and External Slave
A set transmit interrupt flag, UCxTXIFG, indicates that data has moved from UCxTXBUF to the TX shift
register and UCxTXBUF is ready for new data. It does not indicate RX/TX completion.
To receive data into the USCI in master mode, data must be written to UCxTXBUF because receive and
transmit operations operate concurrently.
439
SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, SPI Mode
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