Datasheet

USCI Operation: SPI Mode www.ti.com
16.3 USCI Operation: SPI Mode
In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by
the master. An additional pin, UCxSTE, is provided to enable a device to receive and transmit data and is
controlled by the master.
Three or four signals are used for SPI data exchange:
• UCxSIMO: Slave in, master out
– Master mode: UCxSIMO is the data output line.
– Slave mode: UCxSIMO is the data input line.
• UCxSOMI: Slave out, master in
– Master mode: UCxSOMI is the data input line.
– Slave mode: UCxSOMI is the data output line.
• UCxCLK: USCI SPI clock
– Master mode: UCxCLK is an output.
– Slave mode: UCxCLK is an input.
• UCxSTE: Slave transmit enable
Used in 4-pin mode to allow multiple masters on a single bus. Not used in 3-pin mode. Table 16-1
describes the UCxSTE operation.
Table 16-1. UCxSTE Operation
UCxSTE Active
UCMODEx UCxSTE Slave Master
State
0 Inactive Active
01 High
1 Active Inactive
0 Active Inactive
10 Low
1 Inactive Active
16.3.1 USCI Initialization and Reset
The USCI is reset by a PUC or by the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set,
keeping the USCI in a reset condition. When set, the UCSWRST bit resets the UCxRXIE, UCxTXIE,
UCxRXIFG, UCOE, and UCFE bits and sets the UCxTXIFG flag. Clearing UCSWRST releases the USCI
for operation.
NOTE: Initializing or Re-Configuring the USCI Module
The recommended USCI initialization/re-configuration process is:
1. Set UCSWRST (BIS.B #UCSWRST,&UCxCTL1)
2. Initialize all USCI registers with UCSWRST=1 (including UCxCTL1)
3. Configure ports
4. Clear UCSWRST via software (BIC.B #UCSWRST,&UCxCTL1)
5. Enable interrupts (optional) via UCxRXIE and/or UCxTXIE
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Universal Serial Communication Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
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