Datasheet

ACLK
SMCLK
SMCLK
00
01
10
11
UCSSELx
N/A
Prescaler/Divider
Bit Clock Generator
UCxBRx
16
Receive Shift Register
Receive Buffer UC xRXBUF
Receive State Machine
UCMSB UC7BIT
1
0
UCMST
UCxSOMI
Transmit Buffer UC xTXBUF
Transmit State Machine
Transmit Shift Register
UCMSB UC7BIT
BRCLK
Set UCxRXIFG
Set UCxTXIFG
0
1
UCLISTEN
Clock Direction,
Phase and Polarity
UCCKPH UCCKPL
UCxSIMO
UCxCLK
Set UCOE
Transmit Enable
Control
2
UCMODEx
UCxSTE
Set UCFE
www.ti.com USCI Introduction: SPI Mode
Figure 16-1. USCI Block Diagram: SPI Mode
437
SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, SPI Mode
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