Datasheet

www.ti.com USCI Registers: UART Mode
15.4.11 UCAxABCTL, USCI_Ax Auto Baud Rate Control Register
7 6 5 4 3 2 1 0
Reserved UCDELIMx UCSTOE UCBTOE Reserved UCABDEN
r-0 r-0 rw-0 rw-0 rw-0 rw-0 r-0 rw-0
Reserved Bits 7-6 Reserved
UCDELIMx Bits 5-4 Break/synch delimiter length
00 1 bit time
01 2 bit times
10 3 bit times
11 4 bit times
UCSTOE Bit 3 Synch field time out error
0 No error
1 Length of synch field exceeded measurable time.
UCBTOE Bit 2 Break time out error
0 No error
1 Length of break field exceeded 22 bit times.
Reserved Bit 1 Reserved
UCABDEN Bit 0 Automatic baud rate detect enable
0 Baud rate detection disabled. Length of break and synch field is not measured.
1 Baud rate detection enabled. Length of break and synch field is measured and baud rate settings
are changed accordingly.
15.4.12 IE2, Interrupt Enable Register 2
7 6 5 4 3 2 1 0
UCA0TXIE UCA0RXIE
rw-0 rw-0
Bits 7-2 These bits may be used by other modules (see the device-specific data sheet).
UCA0TXIE Bit 1 USCI_A0 transmit interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCA0RXIE Bit 0 USCI_A0 receive interrupt enable
0 Interrupt disabled
1 Interrupt enabled
15.4.13 IFG2, Interrupt Flag Register 2
7 6 5 4 3 2 1 0
UCA0TXIFG UCA0RXIFG
rw-1 rw-0
Bits 7-2 These bits may be used by other modules (see the device-specific data sheet).
UCA0TXIFG Bit 1 USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF is empty.
0 No interrupt pending
1 Interrupt pending
UCA0RXIFG Bit 0 USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character.
0 No interrupt pending
1 Interrupt pending
433
SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, UART Mode
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