Datasheet

USCI Registers: UART Mode www.ti.com
15.4.7 UCAxRXBUF, USCI_Ax Receive Buffer Register
7 6 5 4 3 2 1 0
UCRXBUFx
rw rw rw rw rw rw rw rw
UCRXBUFx Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shift
register. Reading UCAxRXBUF resets the receive-error bits, the UCADDR or UCIDLE bit, and UCAxRXIFG.
In 7-bit data mode, UCAxRXBUF is LSB justified and the MSB is always reset.
15.4.8 UCAxTXBUF, USCI_Ax Transmit Buffer Register
7 6 5 4 3 2 1 0
UCTXBUFx
rw rw rw rw rw rw rw rw
UCTXBUFx Bits 7-0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift
register and transmitted on UCAxTXD. Writing to the transmit data buffer clears UCAxTXIFG. The MSB of
UCAxTXBUF is not used for 7-bit data and is reset.
15.4.9 UCAxIRTCTL, USCI_Ax IrDA Transmit Control Register
7 6 5 4 3 2 1 0
UCIRTXPLx UCIRTXCLK UCIREN
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
UCIRTXPLx Bits 7-2 Transmit pulse length. Pulse length t
PULSE
= (UCIRTXPLx + 1) / (2 × f
IRTXCLK
)
UCIRTXCLK Bit 1 IrDA transmit pulse clock select
0 BRCLK
1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK
UCIREN Bit 0 IrDA encoder/decoder enable.
0 IrDA encoder/decoder disabled
1 IrDA encoder/decoder enabled
15.4.10 UCAxIRRCTL, USCI_Ax IrDA Receive Control Register
7 6 5 4 3 2 1 0
UCIRRXFLx UCIRRXPL UCIRRXFE
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
UCIRRXFLx Bits 7-2 Receive filter length. The minimum pulse length for receive is given by: t
MIN
= (UCIRRXFLx + 4) / (2 ×
f
IRTXCLK
)
UCIRRXPL Bit 1 IrDA receive input UCAxRXD polarity
0 IrDA transceiver delivers a high pulse when a light pulse is seen
1 IrDA transceiver delivers a low pulse when a light pulse is seen
UCIRRXFE Bit 0 IrDA receive filter enabled
0 Receive filter disabled
1 Receive filter enabled
432
Universal Serial Communication Interface, UART Mode SLAU144J–December 2004–Revised July 2013
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