Datasheet

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USCI Registers: UART Mode

15.4.5 UCAxMCTL, USCI_Ax Modulation Control Register

7 6 5 4 3 2 1 0

UCBRFx UCBRSx UCOS16

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0

UCBRFx Bits 7-4 First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 =

1. Ignored with UCOS16 = 0. Table 15-3 shows the modulation pattern.

UCBRSx Bits 3-1 Second modulation stage select. These bits determine the modulation pattern for BITCLK. Table 15-2 shows

the modulation pattern.

UCOS16 Bit 0 Oversampling mode enabled

0 Disabled

1 Enabled

15.4.6 UCAxSTAT, USCI_Ax Status Register

7 6 5 4 3 2 1 0

UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCADDR UCBUSY

UCIDLE

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-0

UCLISTEN Bit 7 Listen enable. The UCLISTEN bit selects loopback mode.

0 Disabled

1 Enabled. UCAxTXD is internally fed back to the receiver.

UCFE Bit 6 Framing error flag

0 No error

1 Character received with low stop bit

UCOE Bit 5 Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous

character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by

software. Otherwise, it will not function correctly.

0 No error

1 Overrun error occurred

UCPE Bit 4 Parity error flag. When UCPEN = 0, UCPE is read as 0.

0 No error

1 Character received with parity error

UCBRK Bit 3 Break detect flag

0 No break condition

1 Break condition occurred

UCRXERR Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or

more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read.

0 No receive errors detected

1 Receive error detected

UCADDR Bit 1 Address received in address-bit multiprocessor mode.

0 Received character is data

1 Received character is an address

UCIDLE Idle line detected in idle-line multiprocessor mode.

0 No idle line detected

1 Idle line detected

UCBUSY Bit 0 USCI busy. This bit indicates if a transmit or receive operation is in progress.

0 USCI inactive

1 USCI transmitting or receiving

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SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, UART Mode

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