Datasheet

USCI Operation: UART Mode www.ti.com
15.3.14 Using the USCI Module in UART Mode with Low Power Modes
The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When
SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI
module automatically activates it when needed, regardless of the control-bit settings for the clock source.
The clock remains active until the USCI module returns to its idle condition. After the USCI module returns
to the idle condition, control of the clock source reverts to the settings of its control bits. Automatic clock
activation is not provided for ACLK.
When the USCI module activates an inactive clock source, the clock source becomes active for the whole
device and any peripheral configured to use the clock source may be affected. For example, a timer using
SMCLK will increment while the USCI module forces SMCLK active.
15.3.15 USCI Interrupts
The USCI has one interrupt vector for transmission and one interrupt vector for reception.
15.3.15.1 USCI Transmit Interrupt Operation
The UCAxTXIFG interrupt flag is set by the transmitter to indicate that UCAxTXBUF is ready to accept
another character. An interrupt request is generated if UCAxTXIE and GIE are also set. UCAxTXIFG is
automatically reset if a character is written to UCAxTXBUF.
UCAxTXIFG is set after a PUC or when UCSWRST = 1. UCAxTXIE is reset after a PUC or when
UCSWRST = 1.
15.3.15.2 USCI Receive Interrupt Operation
The UCAxRXIFG interrupt flag is set each time a character is received and loaded into UCAxRXBUF. An
interrupt request is generated if UCAxRXIE and GIE are also set. UCAxRXIFG and UCAxRXIE are reset
by a system reset PUC signal or when UCSWRST = 1. UCAxRXIFG is automatically reset when
UCAxRXBUF is read.
Additional interrupt control features include:
• When UCAxRXEIE = 0 erroneous characters will not set UCAxRXIFG.
• When UCDORM = 1, non-address characters will not set UCAxRXIFG in multiprocessor modes. In
plain UART mode, no characters will set UCAxRXIFG.
• When UCBRKIE = 1 a break condition will set the UCBRK bit and the UCAxRXIFG flag.
15.3.15.3 USCI Interrupt Usage
USCI_Ax and USCI_Bx share the same interrupt vectors. The receive interrupt flags UCAxRXIFG and
UCBxRXIFG are routed to one interrupt vector, the transmit interrupt flags UCAxTXIFG and UCBxTXIFG
share another interrupt vector.
Example 15-1 shows an extract of an interrupt service routine to handle data receive interrupts from
USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode.
Example 15-1. Shared Interrupt Vectors Software Example, Data Receive
USCIA0_RX_USCIB0_RX_ISR
BIT.B #UCA0RXIFG, &IFG2 ; USCI_A0 Receive Interrupt?
JNZ USCIA0_RX_ISR
USCIB0_RX_ISR?
; Read UCB0RXBUF (clears UCB0RXIFG)
...
RETI
USCIA0_RX_ISR
; Read UCA0RXBUF (clears UCA0RXIFG)
...
RETI
426
Universal Serial Communication Interface, UART Mode SLAU144J–December 2004–Revised July 2013
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