Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 28 16-Bit 16 MHz I/O number 24

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N/2

Bit Start

BRCLK

Counter

BITCLK

N/2−1 N/2−2

1 N/2 N/2−1 1 N/2 N/2−1

N/2−2

0 N/2 N/2−11

INT(N/2) + m(= 0)

INT(N/2) + m(= 1)

1 0 N/2

Bit Period

EVEN

: INT(N/2)

ODD

: INT(N/2) + R(= 1)

m: corresponding modulation bit

R: Remainder from N/2 division

Majority Vote:

(m= 0)

(m= 1)

USCI Operation: UART Mode

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Timing for each bit is shown in Figure 15-10. For each bit received, a majority vote is taken to determine

the bit value. These samples occur at the N/2 - 1/2, N/2, and N/2 + 1/2 BRCLK periods, where N is the

number of BRCLKs per BITCLK.

Figure 15-10. BITCLK Baud Rate Timing With UCOS16 = 0

Modulation is based on the UCBRSx setting as shown in Table 15-2. A 1 in the table indicates that m = 1

and the corresponding BITCLK period is one BRCLK period longer than a BITCLK period with m = 0. The

modulation wraps around after 8 bits but restarts with each new start bit.

Table 15-2. BITCLK Modulation Pattern

Bit 0

UCBRSx Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

(Start Bit)

0 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0

2 0 1 0 0 0 1 0 0

3 0 1 0 1 0 1 0 0

4 0 1 0 1 0 1 0 1

5 0 1 1 1 0 1 0 1

6 0 1 1 1 0 1 1 1

7 0 1 1 1 1 1 1 1

15.3.9.2 Oversampling Baud Rate Generation

The oversampling mode is selected when UCOS16 = 1. This mode supports sampling a UART bit stream

with higher input clock frequencies. This results in majority votes that are always 1/16 of a bit clock period

apart. This mode also easily supports IrDA pulses with a 3/16 bit-time when the IrDA encoder and decoder

are enabled.

This mode uses one prescaler and one modulator to generate the BITCLK16 clock that is 16 times faster

than the BITCLK. An additional divider and modulator stage generates BITCLK from BITCLK16. This

combination supports fractional divisions of both BITCLK16 and BITCLK for baud rate generation. In this

mode, the maximum USCI baud rate is 1/16 the UART source clock frequency BRCLK. When UCBRx is

set to 0 or 1 the first prescaler and modulator stage is bypassed and BRCLK is equal to BITCLK16.

Modulation for BITCLK16 is based on the UCBRFx setting as shown in Table 15-3. A 1 in the table

indicates that the corresponding BITCLK16 period is one BRCLK period longer than the periods m=0. The

modulation restarts with each new bit timing.

Modulation for BITCLK is based on the UCBRSx setting as shown in Table 15-2 as previously described.

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Universal Serial Communication Interface, UART Mode SLAU144J–December 2004–Revised July 2013

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