Datasheet

[Parity Bit, UCPEN = 1]
[Address Bit, UCMODEx = 10]
Mark
Space
D0 D6 D7 AD PA SP SP
[Optional Bit, Condition]
[2nd Stop Bit, UCSPB = 1]
[8th Data Bit, UC7BIT = 0]
ST
www.ti.com USCI Operation: UART Mode
15.3 USCI Operation: UART Mode
In UART mode, the USCI transmits and receives characters at a bit rate asynchronous to another device.
Timing for each character is based on the selected baud rate of the USCI. The transmit and receive
functions use the same baud rate frequency.
15.3.1 USCI Initialization and Reset
The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is
automatically set, keeping the USCI in a reset condition. When set, the UCSWRST bit resets the
UCAxRXIE, UCAxTXIE, UCAxRXIFG, UCRXERR, UCBRK, UCPE, UCOE, UCFE, UCSTOE and
UCBTOE bits and sets the UCAxTXIFG bit. Clearing UCSWRST releases the USCI for operation.
NOTE: Initializing or Re-Configuring the USCI Module
The recommended USCI initialization/re-configuration process is:
1. Set UCSWRST (BIS.B #UCSWRST,&UCAxCTL1)
2. Initialize all USCI registers with UCSWRST = 1 (including UCAxCTL1)
3. Configure ports.
4. Clear UCSWRST via software (BIC.B #UCSWRST,&UCAxCTL1)
5. Enable interrupts (optional) via UCAxRXIE and/or UCAxTXIE
15.3.2 Character Format
The UART character format, shown in Figure 15-2, consists of a start bit, seven or eight data bits, an
even/odd/no parity bit, an address bit (address-bit mode), and one or two stop bits. The UCMSB bit
controls the direction of the transfer and selects LSB or MSB first. LSB-first is typically required for UART
communication.
Figure 15-2. Character Format
15.3.3 Asynchronous Communication Formats
When two devices communicate asynchronously, no multiprocessor format is required for the protocol.
When three or more devices communicate, the USCI supports the idle-line and address-bit multiprocessor
communication formats.
15.3.3.1 Idle-Line Multiprocessor Format
When UCMODEx = 01, the idle-line multiprocessor format is selected. Blocks of data are separated by an
idle time on the transmit or receive lines as shown in Figure 15-3. An idle receive line is detectedwhen 10
or more continuous ones (marks) are received after the one or two stop bits of a character. The baud rate
generator is switched off after reception of an idle line until the next start edge is detected. When an idle
line is detected the UCIDLE bit is set.
The first character received after an idle period is an address character. The UCIDLE bit is used as an
address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received
character is an address.
413
SLAU144J–December 2004–Revised July 2013 Universal Serial Communication Interface, UART Mode
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