Datasheet

USI Registers www.ti.com
14.3.3 USICKCTL, USI Clock Control Register
7 6 5 4 3 2 1 0
USIDIVx USISSELx USICKPL USISWCLK
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
USIDIVx Bits 7-5 Clock divider select
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
USISSELx Bits 4-2 Clock source select. Not used in slave mode.
000 SCLK (Not used in SPI mode)
001 ACLK
010 SMCLK
011 SMCLK
100 USISWCLK bit
101 TACCR0
110 TACCR1
111 TACCR2 (Reserved on MSP430F20xx devices)
USICKPL Bit 1 Clock polarity select
0 Inactive state is low
1 Inactive state is high
USISWCLK Bit 0 Software clock
0 Input clock is low
1 Input clock is high
14.3.4 USICNT, USI Bit Counter Register
7 6 5 4 3 2 1 0
USISCLREL USI16B USIIFGCC USICNTx
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
USISCLREL Bit 7 SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is
detected.
0 SCL line is held low if USIIFG is set
1 SCL line is released
USI16B Bit 6 16-bit shift register enable
0 8-bit shift register mode. Low byte register USISRL is used.
1 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR
addresses all 16 bits simultaneously.
USIIFGCC Bit 5 USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when
USICNTx is written with a value > 0.
0 USIIFG automatically cleared on USICNTx update
1 USIIFG is not cleared automatically
USICNTx Bits 4-0 USI bit count. The USICNTx bits set the number of bits to be received or transmitted.
408
Universal Serial Interface (USI) SLAU144J–December 2004–Revised July 2013
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