Datasheet

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14.3.2 USICTL1, USI Control Register 1
7 6 5 4 3 2 1 0
USICKPH USII2C USISTTIE USIIE USIAL USISTP USISTTIFG USIIFG
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1
USICKPH Bit 7 Clock phase select
0 Data is changed on the first SCLK edge and captured on the following edge.
1 Data is captured on the first SCLK edge and changed on the following edge.
USII2C Bit 6 I
2
C mode enable
0 I
2
C mode disabled
1 I
2
C mode enabled
USISTTIE Bit 5 START condition interrupt-enable
0 Interrupt on START condition disabled
1 Interrupt on START condition enabled
USIIE Bit 4 USI counter interrupt enable
0 Interrupt disabled
1 Interrupt enabled
USIAL Bit 3 Arbitration lost
0 No arbitration lost condition
1 Arbitration lost
USISTP Bit 2 STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when
USIIFGCC = 0.
0 No STOP condition received
1 STOP condition received
USISTTIFG Bit 1 START condition interrupt flag
0 No START condition received. No interrupt pending.
1 START condition received. Interrupt pending.
USIIFG Bit 0 USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a
value > 0 when USIIFGCC = 0.
0 No interrupt pending
1 Interrupt pending
407
SLAU144J–December 2004–Revised July 2013 Universal Serial Interface (USI)
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