Datasheet

USI Registers

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14.3.1 USICTL0, USI Control Register 0

7 6 5 4 3 2 1 0

USIPE7 USIPE6 USIPE5 USILSB USIMST USIGE USIOE USISWRST

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1

USIPE7 Bit 7 USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I

C mode.

0 USI function disabled

1 USI function enabled

USIPE6 Bit 6 USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I

C mode.

0 USI function disabled

1 USI function enabled

USIPE5 Bit 5 USI SCLK port enable. Input in SPI slave mode, or I

C mode, output in SPI master mode.

0 USI function disabled

1 USI function enabled

USILSB Bit 4 LSB first select. This bit controls the direction of the receive and transmit shift register.

0 MSB first

1 LSB first

USIMST Bit 3 Master select

0 Slave mode

1 Master mode

USIGE Bit 2 Output latch control

0 Output latch enable depends on shift clock

1 Output latch always enabled and transparent

USIOE Bit 1 Data output enable

0 Output disabled

1 Output enabled

USISWRST Bit 0 USI software reset

0 USI released for operation.

1 USI logic held in reset state.

406

Universal Serial Interface (USI) SLAU144J–December 2004–Revised July 2013

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