Datasheet

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14.2.4.4 I
2
C Receiver
In I
2
C receiver mode the output must be disabled by clearing USIOE and the USI module is prepared for
reception by writing 8 into USICNTx. This clears USIIFG and SCL is generated in master mode or
released from being held low in slave mode. The USIIFG bit will be set after 8 clocks. This stops the clock
signal on SCL in master mode or holds SCL low at the next low phase in slave mode.
To transmit an acknowledge or no-acknowledge bit, the MSB of the shift register is loaded with 0 or 1, the
USIOE bit is set with software to enable the output, and 1 is written to the USICNTx bits. As soon as the
MSB bit is shifted out, USIIFG will be become set and the module can be prepared for the reception of the
next I
2
C data byte.
; Generate ACK
BIS.B #USIOE,&USICTL0 ; SDA output
MOV.B #00h,&USISRL ; MSB = 0
MOV.B #01h,&USICNT ; USICNTx = 1
TEST_USIIFG
BIT.B #USIIFG,&USICTL1 ; Test USIIFG
JZ TEST_USIIFG
...continue...
; Generate NACK
BIS.B #USIOE,&USICTL0 ; SDA output
MOV.B #0FFh,&USISRL ; MSB = 1
MOV.B #01h,&USICNT ; USICNTx = 1
TEST_USIIFG
BIT.B #USIIFG,&USICTL1 ; Test USIIFG
JZ TEST_USIIFG
...continue...
14.2.4.5 START Condition
A START condition is a high-to-low transition on SDA while SCL is high. The START condition can be
generated by setting the MSB of the shift register to 0. Setting the USIGE and USIOE bits makes the
output latch transparent and the MSB of the shift register is immediately presented to SDA and pulls the
line low. Clearing USIGE resumes the clocked-latch function and holds the 0 on SDA until data is shifted
out with SCL.
; Generate START
MOV.B #000h,&USISRL ; MSB = 0
BIS.B #USIGE+USIOE,&USICTL0 ; Latch/SDA output enabled
BIC.B #USIGE,&USICTL0 ; Latch disabled
...continue...
14.2.4.6 STOP Condition
A STOP condition is a low-to-high transition on SDA while SCL is high. To finish the acknowledgment bit
and pull SDA low to prepare the STOP condition generation requires clearing the MSB in the shift register
and loading 1 into USICNTx. This will generate a low pulse on SCL and during the low phase SDA is
pulled low. SCL stops in the idle, or high, state since the module is in master mode. To generate the low-
to-high transition, the MSB is set in the shift register and USICNTx is loaded with 1. Setting the USIGE
and USIOE bits makes the output latch transparent and the MSB of USISRL releases SDA to the idle
state. Clearing USIGE stores the MSB in the output latch and the output is disabled by clearing USIOE.
SDA remains high until a START condition is generated because of the external pullup.
; Generate STOP
BIS.B #USIOE,&USICTL0 ; SDA=output
MOV.B #000h,&USISRL ; MSB = 0
MOV.B #001h,&USICNT ; USICNT = 1 for one clock
TEST_USIIFG
BIT.B #USIIFG,&USICTL1 ; Test USIIFG
JZ test_USIIFG ;
MOV.B #0FFh,&USISRL ; USISRL = 1 to drive SDA high
BIS.B #USIGE,&USICTL0 ; Transparent latch enabled
BIC.B #USIGE+USIOE,&USICTL; Latch/SDA output disabled
...continue...
403
SLAU144J–December 2004–Revised July 2013 Universal Serial Interface (USI)
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