Datasheet

Transmit data in memory

USISRL

Received data in memory

Transmit data in memory

USISRL

Received data in memory

7-bit SPI Mode, MSB first

7-bit SPI Mode, LSB first

USISRL

TX TX

Shift with software

Move

Shift with software

7-bit Data

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USI Operation

14.2.3.3 USISR Operation

The 16-bit USISR is made up of two 8-bit registers, USISRL and USISRH. Control bit USI16B selects the

number of bits of USISR that are used for data transmit and receive. When USI16B = 0, only the lower 8

bits, USISRL, are used.

To transfer < 8 bits, the data must be loaded into USISRL such that unused bits are not shifted out. The

data must be MSB- or LSB-aligned depending on USILSB. Figure 14-4 shows an example of 7-bit data

handling.

Figure 14-4. Data Adjustments for 7-Bit SPI Data

When USI16B = 1, all 16 bits are used for data handling. When using USISR to access both USISRL and

USISRH, the data needs to be properly adjusted when < 16 bits are used in the same manner as shown

in Figure 14-4.

14.2.3.4 SPI Interrupts

There is one interrupt vector associated with the USI module, and one interrupt flag, USIIFG, relevant for

SPI operation. When USIIE and the GIE bit are set, the interrupt flag will generate an interrupt request.

USIIFG is set when USICNTx becomes zero, either by counting or by directly writing 0 to the USICNTx

bits. USIIFG is cleared by writing a value > 0 to the USICNTx bits when USIIFGCC = 0, or directly by

software.

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SLAU144J–December 2004–Revised July 2013 Universal Serial Interface (USI)

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