Datasheet

USI
CKPH
USI
CKPL
USICNTx
SCLK
SCLK
SCLK
SCLK
SDO/SDI
SDO/SDI
USIIFG
0
1
0
0
01
1 1
0 X
1 X
MSB
MSB
8 7 6 5 4 3 2 1
LSB
LSB
00
Load USICNTx
USI Operation www.ti.com
14.2.3 SPI Mode
The USI module is configured in SPI mode when USII2C = 0. Control bit USICKPL selects the inactive
level of the SPI clock while USICKPH selects the clock edge on which SDO is updated and SDI is
sampled. Figure 14-3 shows the clock/data relationship for an 8-bit, MSB-first transfer. USIPE5, USIPE6,
and USIPE7 must be set to enable the SCLK, SDO, and SDI port functions.
Figure 14-3. SPI Timing
14.2.3.1 SPI Master Mode
The USI module is configured as SPI master by setting the master bit USIMST and clearing the I
2
C bit
USII2C. Since the master provides the clock to the slave(s) an appropriate clock source needs to be
selected and SCLK configured as output. When USIPE5 = 1, SCLK is automatically configured as an
output.
When USIIFG = 0 and USICNTx > 0, clock generation is enabled and the master will begin clocking in/out
data using USISR.
Received data must be read from the shift register before new data is written into it for transmission. In a
typical application, the USI software will read received data from USISR, write new data to be transmitted
to USISR, and enable the module for the next transfer by writing the number of bits to be transferred to
USICNTx.
14.2.3.2 SPI Slave Mode
The USI module is configured as SPI slave by clearing the USIMST and the USII2C bits. In this mode,
when USIPE5 = 1 SCLK is automatically configured as an input and the USI receives the clock externally
from the master.
If the USI is to transmit data, the shift register must be loaded with the data before the master provides the
first clock edge. The output must be enabled by setting USIOE. When USICKPH = 1, the MSB will be
visible on SDO immediately after loading the shift register.
The SDO pin can be disabled by clearing the USIOE bit. This is useful if the slave is not addressed in an
environment with multiple slaves on the bus.
Once all bits are received, the data must be read from USISR and new data loaded into USISR before the
next clock edge from the master. In a typical application, after receiving data, the USI software will read
the USISR register, write new data to USISR to be transmitted, and enable the USI module for the next
transfer by writing the number of bits to be transferred to USICNTx.
400
Universal Serial Interface (USI) SLAU144J–December 2004–Revised July 2013
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