Datasheet

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6.2.4 Stopping DMA Transfers ....................................................................................... 298
6.2.5 DMA Channel Priorities ........................................................................................ 299
6.2.6 DMA Transfer Cycle Time ..................................................................................... 299
6.2.7 Using DMA With System Interrupts ........................................................................... 299
6.2.8 DMA Controller Interrupts ...................................................................................... 300
6.2.9 Using the USCI_B I
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C Module with the DMA Controller ................................................... 300
6.2.10 Using ADC12 with the DMA Controller ...................................................................... 301
6.2.11 Using DAC12 With the DMA Controller ..................................................................... 301
6.2.12 Writing to Flash With the DMA Controller .................................................................. 301
6.3 DMA Registers ........................................................................................................... 302
6.3.1 DMACTL0, DMA Control Register 0 .......................................................................... 303
6.3.2 DMACTL1, DMA Control Register 1 .......................................................................... 303
6.3.3 DMAxCTL, DMA Channel x Control Register ............................................................... 304
6.3.4 DMAxSA, DMA Source Address Register ................................................................... 305
6.3.5 DMAxDA, DMA Destination Address Register .............................................................. 306
6.3.6 DMAxSZ, DMA Size Address Register ....................................................................... 306
6.3.7 DMAIV, DMA Interrupt Vector Register ...................................................................... 307
7 Flash Memory Controller .................................................................................................. 308
7.1 Flash Memory Introduction ............................................................................................. 309
7.2 Flash Memory Segmentation ........................................................................................... 309
7.2.1 SegmentA ........................................................................................................ 310
7.3 Flash Memory Operation ................................................................................................ 311
7.3.1 Flash Memory Timing Generator ............................................................................. 311
7.3.2 Erasing Flash Memory ......................................................................................... 312
7.3.3 Writing Flash Memory .......................................................................................... 315
7.3.4 Flash Memory Access During Write or Erase ............................................................... 320
7.3.5 Stopping a Write or Erase Cycle .............................................................................. 321
7.3.6 Marginal Read Mode ........................................................................................... 321
7.3.7 Configuring and Accessing the Flash Memory Controller ................................................. 321
7.3.8 Flash Memory Controller Interrupts ........................................................................... 321
7.3.9 Programming Flash Memory Devices ........................................................................ 321
7.4 Flash Memory Registers ................................................................................................ 323
7.4.1 FCTL1, Flash Memory Control Register ..................................................................... 324
7.4.2 FCTL2, Flash Memory Control Register ..................................................................... 324
7.4.3 FCTL3, Flash Memory Control Register ..................................................................... 325
7.4.4 FCTL4, Flash Memory Control Register ..................................................................... 326
7.4.5 IE1, Interrupt Enable Register 1 .............................................................................. 326
8 Digital I/O ........................................................................................................................ 327
8.1 Digital I/O Introduction ................................................................................................... 328
8.2 Digital I/O Operation ..................................................................................................... 328
8.2.1 Input Register PxIN ............................................................................................. 328
8.2.2 Output Registers PxOUT ....................................................................................... 328
8.2.3 Direction Registers PxDIR ..................................................................................... 329
8.2.4 Pullup/Pulldown Resistor Enable Registers PxREN ........................................................ 329
8.2.5 Function Select Registers PxSEL and PxSEL2 ............................................................. 329
8.2.6 Pin Oscillator ..................................................................................................... 330
8.2.7 P1 and P2 Interrupts ............................................................................................ 331
8.2.8 Configuring Unused Port Pins ................................................................................. 332
8.3 Digital I/O Registers ..................................................................................................... 333
9 Supply Voltage Supervisor (SVS) ....................................................................................... 335
9.1 Supply Voltage Supervisor (SVS) Introduction ....................................................................... 336
9.2 SVS Operation ........................................................................................................... 337
9.2.1 Configuring the SVS ............................................................................................ 337
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Contents SLAU144J–December 2004–Revised July 2013
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