Datasheet

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14.2 USI Operation
The USI module is a shift register and bit counter that includes logic to support SPI and I
2
C
communication. The USI shift register (USISR) is directly accessible by software and contains the data to
be transmitted or the data that has been received.
The bit counter counts the number of sampled bits and sets the USI interrupt flag USIIFG when the
USICNTx value becomes zero, either by decrementing or by directly writing zero to the USICNTx bits.
Writing USICNTx with a value > 0 automatically clears USIIFG when USIIFGCC = 0, otherwise USIIFG is
not affected. The USICNTx bits stop decrementing when they become 0. They will not underflow to 0FFh.
Both the counter and the shift register are driven by the same shift clock. On a rising shift clock edge,
USICNTx decrements and USISR samples the next bit input. The latch connected to the shift register’s
output delays the change of the output to the falling edge of shift clock. It can be made transparent by
setting the USIGE bit. This setting will immediately output the MSB or LSB of USISR to the SDO pin,
depending on the USILSB bit.
14.2.1 USI Initialization
While the USI software reset bit, USISWRST, is set, the flags USIIFG, USISTTIFG, USISTP, and USIAL
will be held in their reset state. USISR and USICNTx are not clocked and their contents are not affected.
In I
2
C mode, the SCL line is also released to the idle state by the USI hardware.
To activate USI port functionality the corresponding USIPEx bits in the USI control register must be set.
This will select the USI function for the pin and maintains the PxIN and PxIFG functions for the pin as well.
With this feature, the port input levels can be read via the PxIN register by software and the incoming data
stream can generate port interrupts on data transitions. This is useful, for example, to generate a port
interrupt on a START edge.
14.2.2 USI Clock Generation
The USI clock generator contains a clock selection multiplexer, a divider, and the ability to select the clock
polarity as shown in the block diagrams Figure 14-1 and Figure 14-2.
The clock source can be selected from the internal clocks ACLK or SMCLK, from an external clock SCLK,
as well as from the capture/compare outputs of Timer_A. In addition, it is possible to clock the module by
software using the USISWCLK bit when USISSELx = 100.
The USIDIVx bits can be used to divide the selected clock by a power of 2 up to 128. The generated
clock, USICLK, is stopped when USIIFG = 1 or when the module operates in slave mode.
The USICKPL bit is used to select the polarity of USICLK. When USICKPL = 0, the inactive level of
USICLK is low. When USICKPL = 1 the inactive level of USICLK is high.
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SLAU144J–December 2004–Revised July 2013 Universal Serial Interface (USI)
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