Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 28 16-Bit 16 MHz I/O number 24

391

392

393

394

395

396

397

398

399

400

www.ti.com

Timer_B Registers

13.3.1 Timer_B Control Register TBCTL

15 14 13 12 11 10 9 8

Unused TBCLGRPx CNTLx Unused TBSSELx

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

7 6 5 4 3 2 1 0

IDx MCx Unused TBCLR TBIE TBIFG

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) w-(0) rw-(0) rw-(0)

Unused Bit 15 Unused

TBCLGRP Bit 14-13 TBCLx group

00 Each TBCLx latch loads independently

01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update)

TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update)

TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update)

TBCL0 independent

10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update)

TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update)

TBCL0 independent

11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 (TBCCR1 CLLDx bits control the update)

CNTLx Bits 12-11 Counter length

00 16-bit, TBR(max) = 0FFFFh

01 12-bit, TBR(max) = 0FFFh

10 10-bit, TBR(max) = 03FFh

11 8-bit, TBR(max) = 0FFh

Unused Bit 10 Unused

TBSSELx Bits 9-8 Timer_B clock source select.

00 TBCLK

01 ACLK

10 SMCLK

11 INCLK (INCLK is device-specific and is often assigned to the inverted TBCLK) (see the device-

specific data sheet)

IDx Bits 7-6 Input divider. These bits select the divider for the input clock.00 /101 /210 /411 /8

MCx Bits 5-4 Mode control. Setting MCx = 00h when Timer_B is not in use conserves power.

00 Stop mode: the timer is halted

01 Up mode: the timer counts up to TBCL0

10 Continuous mode: the timer counts up to the value set by CNTLx

11 Up/down mode: the timer counts up to TBCL0 and down to 0000h

Unused Bit 3 Unused

TBCLR Bit 2 Timer_B clear. Setting this bit resets TBR, the clock divider, and the count direction. The TBCLR bit is

automatically reset and is always read as zero.

TBIE Bit 1 Timer_B interrupt enable. This bit enables the TBIFG interrupt request.

0 Interrupt disabled

1 Interrupt enabled

TBIFG Bit 0 Timer_B interrupt flag.

0 No interrupt pending

1 Interrupt pending

391

SLAU144J–December 2004–Revised July 2013 Timer_B

Submit Documentation Feedback