Datasheet

Second
Capture
Taken
COV = 1
Capture
Taken
No
Capture
Taken
Read
Taken
Capture
Clear Bit COV
in Register TBCCTLx
Idle
Idle
Capture
Capture Read and No Capture
Capture
Capture ReadCapture
Capture
Timer_B Operation www.ti.com
Overflow logic is provided in each capture/compare register to indicate if a second capture was performed
before the value from the first capture was read. Bit COV is set when this occurs as shown in Figure 13-
11. COV must be reset with software.
Figure 13-11. Capture Cycle
13.2.4.1.1 Capture Initiated by Software
Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then
sets bit CCIS1=1 and toggles bit CCIS0 to switch the capture signal between V
CC
and GND, initiating a
capture each time CCIS0 changes state:
MOV #CAP+SCS+CCIS1+CM_3,&TBCCTLx ; Setup TBCCTLx
XOR #CCIS0, &TBCCTLx ; TBCCTLx = TBR
382
Timer_B SLAU144J–December 2004–Revised July 2013
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