Datasheet

n−2 n−1
Timer Clock
Timer
Set TBCCRx CCIFG
n+1 n+3 n+4
CCI
Capture
n+2n
TBIFG
0h
TBR
(max)
Output Mode 2:Toggle/Reset
Output Mode 6:Toggle/Set
TBCL0
TBCL1
EQU1
TBIFG
Interrupt Events
EQU1
EQU0
EQU1 EQU1
EQU0
TBCL3
EQU3 EQU3EQU3 EQU3
Dead Time
www.ti.com Timer_B Operation
The ability to simultaneously load grouped compare latches assures the dead times.
Figure 13-9. Output Unit in Up/Down Mode
13.2.4 Capture/Compare Blocks
Three or seven identical capture/compare blocks, TBCCRx, are present in Timer_B. Any of the blocks
may be used to capture the timer data or to generate time intervals.
13.2.4.1 Capture Mode
The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used
for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to
external pins or internal signals and are selected with the CCISx bits. The CMx bits select the capture
edge of the input signal as rising, falling, or both. A capture occurs on the selected edge of the input
signal. If a capture is performed:
• The timer value is copied into the TBCCRx register
• The interrupt flag CCIFG is set
The input signal level can be read at any time via the CCI bit. MSP430x2xx family devices may have
different signals connected to CCIxA and CCIxB. Refer to the device-specific data sheet for the
connections of these signals.
The capture signal can be asynchronous to the timer clock and cause a race condition. Setting the SCS
bit will synchronize the capture with the next timer clock. Setting the SCS bit to synchronize the capture
signal with the timer clock is recommended. This is illustrated in Figure 13-10.
Figure 13-10. Capture Signal (SCS = 1)
381
SLAU144J–December 2004–Revised July 2013 Timer_B
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