Datasheet

TBCL0−1 TBCL0 TBCL0−1
Timer Clock
Timer
Set TBIFG
Set TBCCR0 CCIFG
TBCL0−2 1h 0h 1h
Up/Down
0h
TBCL0
Timer_B Operation www.ti.com
Figure 13-7. Up/Down Mode
The count direction is latched. This allows the timer to be stopped and then restarted in the same direction
it was counting before it was stopped. If this is not desired, the TBCLR bit must be used to clear the
direction. The TBCLR bit also clears the TBR value and the clock divider.
In up/down mode, the TBCCR0 CCIFG interrupt flag and the TBIFG interrupt flag are set only once during
the period, separated by 1/2 the timer period. The TBCCR0 CCIFG interrupt flag is set when the timer
counts from TBCL0-1 to TBCL0, and TBIFG is set when the timer completes counting down from 0001h to
0000h. Figure 13-8 shows the flag set cycle.
Figure 13-8. Up/Down Mode Flag Setting
13.2.3.6 Changing the Value of Period Register TBCL0
When changing TBCL0 while the timer is running, and counting in the down direction, and when the
TBCL0 load event is immediate, the timer continues its descent until it reaches zero. The value in
TBCCR0 is latched into TBCL0 immediately; however, the new period takes effect after the counter counts
down to zero.
If the timer is counting in the up direction when the new period is latched into TBCL0, and the new period
is greater than or equal to the old period, or greater than the current count value, the timer counts up to
the new period before counting down. When the timer is counting in the up direction, and the new period
is less than the current count value when TBCL0 is loaded, the timer begins counting down. However, one
additional count may occur before the counter begins counting down.
13.2.3.7 Use of the Up/Down Mode
The up/down mode supports applications that require dead times between output signals (see section
Timer_B Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must
never be in a high state simultaneously. In the example shown in Figure 13-9 the t
dead
is:
t
dead
= t
timer
× (TBCL1 - TBCL3)
Where,
t
dead
= Time during which both outputs need to be inactive
t
timer
= Cycle time of the timer clock
TBCLx = Content of compare latch x
380
Timer_B SLAU144J–December 2004–Revised July 2013
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