Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 28 16-Bit 16 MHz I/O number 24

www.ti.com

Interrupts

2.2.4 Interrupt Vectors

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to

0FFC0h, as described in Table 2-1. A vector is programmed by the user with the 16-bit address of the

corresponding interrupt service routine. See the device-specific data sheet for the complete interrupt

vector list.

It is recommended to provide an interrupt service routine for each interrupt vector that is assigned to a

module. A dummy interrupt service routine can consist of just the RETI instruction and several interrupt

vectors can point to it.

Unassigned interrupt vectors can be used for regular program code if necessary.

Some module enable bits, interrupt enable bits, and interrupt flags are located in the SFRs. The SFRs are

located in the lower address range and are implemented in byte format. SFRs must be accessed using

byte instructions. See the device-specific data sheet for the SFR configuration.

Table 2-1. Interrupt Sources, Flags, and Vectors

Interrupt Source Interrupt Flag System Interrupt Word Address Priority

PORIFG

Power-up, external reset, watchdog, flash RSTIFG

Reset 0FFFEh 31, highest

password, illegal instruction fetch WDTIFG

KEYV

NMIIFG (non)-maskable

NMI, oscillator fault, flash memory access

OFIFG (non)-maskable 0FFFCh 30

violation

ACCVIFG (non)-maskable

device-specific 0FFFAh 29

device-specific 0FFF8h 28

device-specific 0FFF6h 27

Watchdog timer WDTIFG maskable 0FFF4h 26

device-specific 0FFF2h 25

device-specific 0FFF0h 24

device-specific 0FFEEh 23

device-specific 0FFECh 22

device-specific 0FFEAh 21

device-specific 0FFE8h 20

device-specific 0FFE6h 19

device-specific 0FFE4h 18

device-specific 0FFE2h 17

device-specific 0FFE0h 16

device-specific 0FFDEh 15

device-specific 0FFDCh 14

device-specific 0FFDAh 13

device-specific 0FFD8h 12

device-specific 0FFD6h 11

device-specific 0FFD4h 10

device-specific 0FFD2h 9

device-specific 0FFD0h 8

device-specific 0FFCEh 7

device-specific 0FFCCh 6

device-specific 0FFCAh 5

device-specific 0FFC8h 4

device-specific 0FFC6h 3

device-specific 0FFC4h 2

device-specific 0FFC2h 1

device-specific 0FFC0h 0, lowest

SLAU144J–December 2004–Revised July 2013 System Resets, Interrupts, and Operating Modes

Submit Documentation Feedback