Datasheet

CCR0−1 CCR0 CCR0−1
Timer Clock
Timer
Set TAIFG
Set TACCR0 CCIFG
CCR0−2 1h 0h
Up/Down
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Figure 12-8. Up/Down Mode Flag Setting
12.2.3.6 Changing the Period Register TACCR0
When changing TACCR0 while the timer is running, and counting in the down direction, the timer
continues its descent until it reaches zero. The value in TACCR0 is latched into TACL0 immediately,
however the new period takes effect after the counter counts down to zero.
When the timer is counting in the up direction, and the new period is greater than or equal to the old
period, or greater than the current count value, the timer counts up to the new period before counting
down. When the timer is counting in the up direction, and the new period is less than the current count
value, the timer begins counting down. However, one additional count may occur before the counter
begins counting down.
12.2.3.7 Use of the Up/Down Mode
The up/down mode supports applications that require dead times between output signals (See section
Timer_A Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must
never be in a high state simultaneously. In the example shown in Figure 12-9 the t
dead
is:
t
dead
= t
timer
(TACCR1 – TACCR2)
Where,
t
dead
= Time during which both outputs need to be inactive
t
timer
= Cycle time of the timer clock
TACCRx = Content of capture/compare register x
The TACCRx registers are not buffered. They update immediately when written to. Therefore, any
required dead time will not be maintained automatically.
361
SLAU144J–December 2004–Revised July 2013 Timer_A
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