Datasheet

FFFEh FFFFh 0h
Timer Clock
Timer
Set TAIFG
1h FFFEh FFFFh 0h
0h
0FFFFh
CCR0−1 CCR0 0h
Timer Clock
Timer
Set TAIFG
Set TACCR0 CCIFG
1h CCR0−1 CCR0 0h
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Figure 12-3. Up Mode Flag Setting
12.2.3.2 Changing the Period Register TACCR0
When changing TACCR0 while the timer is running, if the new period is greater than or equal to the old
period, or greater than the current count value, the timer counts up to the new period. If the new period is
less than the current count value, the timer rolls to zero. However, one additional count may occur before
the counter rolls to zero.
12.2.3.3 Continuous Mode
In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in
Figure 12-4. The capture/compare register TACCR0 works the same way as the other capture/compare
registers.
Figure 12-4. Continuous Mode
The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero. Figure 12-5 shows the flag set
cycle.
Figure 12-5. Continuous Mode Flag Setting
12.2.3.4 Use of the Continuous Mode
The continuous mode can be used to generate independent time intervals and output frequencies. Each
time an interval is completed, an interrupt is generated. The next time interval is added to the TACCRx
register in the interrupt service routine. Figure 12-6 shows two separate time intervals t
0
and t
1
being
added to the capture/compare registers. In this usage, the time interval is controlled by hardware, not
software, without impact from interrupt latency. Up to three independent time intervals or output
frequencies can be generated using all three capture/compare registers.
359
SLAU144J–December 2004–Revised July 2013 Timer_A
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