Datasheet

0h
0FFFFh
TACCR0
Timer_A Operation www.ti.com
NOTE: Modifying Timer_A Registers
It is recommended to stop the timer before modifying its operation (with exception of the
interrupt enable, and interrupt flag) to avoid errant operating conditions.
When the timer clock is asynchronous to the CPU clock, any read from TAR should occur
while the timer is not operating or the results may be unpredictable. Alternatively, the timer
may be read multiple times while operating, and a majority vote taken in software to
determine the correct reading. Any write to TAR will take effect immediately.
12.2.1.1 Clock Source Select and Divider
The timer clock can be sourced from ACLK, SMCLK, or externally via TACLK or INCLK. The clock source
is selected with the TASSELx bits. The selected clock source may be passed directly to the timer or
divided by 2, 4, or 8, using the IDx bits. The timer clock divider is reset when TACLR is set.
12.2.2 Starting the Timer
The timer may be started, or restarted in the following ways:
• The timer counts when MCx > 0 and the clock source is active.
• When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0. The
timer may then be restarted by writing a nonzero value to TACCR0. In this scenario, the timer starts
incrementing in the up direction from zero.
12.2.3 Timer Mode Control
The timer has four modes of operation as described in Table 12-1: stop, up, continuous, and up/down.
The operating mode is selected with the MCx bits.
Table 12-1. Timer Modes
MCx Mode Description
00 Stop The timer is halted.
01 Up The timer repeatedly counts from zero to the value of TACCR0.
10 Continuous The timer repeatedly counts from zero to 0FFFFh.
11 Up/down The timer repeatedly counts from zero up to the value of TACCR0 and back down to zero.
12.2.3.1 Up Mode
The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly
counts up to the value of compare register TACCR0, which defines the period, as shown in Figure 12-2.
The number of timer counts in the period is TACCR0+1. When the timer value equals TACCR0 the timer
restarts counting from zero. If up mode is selected when the timer value is greater than TACCR0, the
timer immediately restarts counting from zero.
Figure 12-2. Up Mode
The TACCR0 CCIFG interrupt flag is set when the timer counts to the TACCR0 value. The TAIFG
interrupt flag is set when the timer counts from TACCR0 to zero. Figure 12-3 shows the flag set cycle.
358
Timer_A SLAU144J–December 2004–Revised July 2013
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated