Datasheet

Comparator 2
CCI
15 0
CCISx
OUTMODx
Capture
Mode
CMx
Sync
SCS
COVlogic
Output
Unit2
D
Set
Q
EQU0
OUT
OUT2 Signal
Reset
GND
VCC
CCI2A
CCI2B
EQU2
Divider
1/2/4/8
Count
Mode
16−bit Timer
TAR
RC
ACLK
SMCLK
TACLK
INCLK
Set TAIFG
15 0
TASSELx
MCxIDx
00
01
10
11
Clear
Timer Clock
EQU0
Timer Clock
Timer Clock
SCCI Y
A
EN
CCR1
POR
TACLR
CCR0
Timer Block
00
01
10
11
CAP
1
0
1
0
CCR2
Set TACCR2
CCIFG
TACCR2
www.ti.com Timer_A Operation
Figure 12-1. Timer_A Block Diagram
12.2 Timer_A Operation
The Timer_A module is configured with user software. The setup and operation of Timer_A is discussed in
the following sections.
12.2.1 16-Bit Timer Counter
The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) with
each rising edge of the clock signal. TAR can be read or written with software. Additionally, the timer can
generate an interrupt when it overflows.
TAR may be cleared by setting the TACLR bit. Setting TACLR also clears the clock divider and count
direction for up/down mode.
357
SLAU144J–December 2004–Revised July 2013 Timer_A
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated