Datasheet

OP2 138h
16 x 16 Multipiler
32−bitAdder
32−bit Multiplexer
015
15 0
Multiplexer
C
MPY 130h
MPYS 132h
MAC 134h
MACS 136h
RESHI 13Ch
S
SUMEXT 13Eh
OP1
RESLO 13Ah
031
MPY, MPYS MAC, MACS
MACS MPYS
MAC
MPY = 0000
rw
rw
rwrw015
r
Accessible
Register
Hardware Multiplier Introduction www.ti.com
11.1 Hardware Multiplier Introduction
The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do
not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and
read with CPU instructions.
The hardware multiplier supports:
• Unsigned multiply
• Signed multiply
• Unsigned multiply accumulate
• Signed multiply accumulate
• 16x16 bits, 16x8 bits, 8x16 bits, 8x8 bits
The hardware multiplier block diagram is shown in Figure 11-1.
Figure 11-1. Hardware Multiplier Block Diagram
11.2 Hardware Multiplier Operation
The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and
signed multiply accumulate operations. The type of operation is selected by the address the first operand
is written to.
The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers,
RESLO, RESHI, and SUMEXT. RESLO stores the low word of the result, RESHI stores the high word of
the result, and SUMEXT stores information about the result. The result is ready in three MCLK cycles and
can be read with the next instruction after writing to OP2, except when using an indirect addressing mode
to access the result. When using indirect addressing for the result, a NOP is required before the result is
ready.
350
Hardware Multiplier SLAU144J–December 2004–Revised July 2013
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