Datasheet

www.ti.com Watchdog Timer+ Registers
10.3.1 WDTCTL, Watchdog Timer+ Register
15 14 13 12 11 10 9 8
WDTPW, Read as 069h
Must be written as 05Ah
7 6 5 4 3 2 1 0
WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx
rw-0 rw-0 rw-0 rw-0 r0(w) rw-0 rw-0 rw-0
WDTPW Bits 15-8 Watchdog timer+ password. Always read as 069h. Must be written as 05Ah, or a PUC is generated.
WDTHOLD Bit 7 Watchdog timer+ hold. This bit stops the watchdog timer+. Setting WDTHOLD = 1 when the WDT+ is not in
use conserves power.
0 Watchdog timer+ is not stopped
1 Watchdog timer+ is stopped
WDTNMIES Bit 6 Watchdog timer+ NMI edge select. This bit selects the interrupt edge for the NMI interrupt when WDTNMI =
1. Modifying this bit can trigger an NMI. Modify this bit when WDTIE = 0 to avoid triggering an accidental
NMI.
0 NMI on rising edge
1 NMI on falling edge
WDTNMI Bit 5 Watchdog timer+ NMI select. This bit selects the function for the RST/NMI pin.
0 Reset function
1 NMI function
WDTTMSEL Bit 4 Watchdog timer+ mode select
0 Watchdog mode
1 Interval timer mode
WDTCNTCL Bit 3 Watchdog timer+ counter clear. Setting WDTCNTCL = 1 clears the count value to 0000h. WDTCNTCL is
automatically reset.
0 No action
1 WDTCNT = 0000h
WDTSSEL Bit 2 Watchdog timer+ clock source select
0 SMCLK
1 ACLK
WDTISx Bits 1-0 Watchdog timer+ interval select. These bits select the watchdog timer+ interval to set the WDTIFG flag
and/or generate a PUC.
00 Watchdog clock source /32768
01 Watchdog clock source /8192
10 Watchdog clock source /512
11 Watchdog clock source /64
347
SLAU144J–December 2004–Revised July 2013 Watchdog Timer+ (WDT+)
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