Datasheet

www.ti.com

Watchdog Timer+ Operation

10.2.5 Watchdog Timer+ Clock Fail-Safe Operation

The WDT+ module provides a fail-safe clocking feature assuring the clock to the WDT+ cannot be

disabled while in watchdog mode. This means the low-power modes may be affected by the choice for the

WDT+ clock. For example, if ACLK is the WDT+ clock source, LPM4 will not be available, because the

WDT+ will prevent ACLK from being disabled. Also, if ACLK or SMCLK fail while sourcing the WDT+, the

WDT+ clock source is automatically switched to MCLK. In this case, if MCLK is sourced from a crystal,

and the crystal has failed, the fail-safe feature will activate the DCO and use it as the source for MCLK.

When the WDT+ module is used in interval timer mode, there is no fail-safe feature for the clock source.

10.2.6 Operation in Low-Power Modes

The MSP430 devices have several low-power modes. Different clock signals are available in different low-

power modes. The requirements of the user’s application and the type of clocking used determine how the

WDT+ should be configured. For example, the WDT+ should not be configured in watchdog mode with

SMCLK as its clock source if the user wants to use low-power mode 3 because the WDT+ will keep

SMCLK enabled for its clock source, increasing the current consumption of LPM3. When the watchdog

timer+ is not required, the WDTHOLD bit can be used to hold the WDTCNT, reducing power consumption.

10.2.7 Software Examples

Any write operation to WDTCTL must be a word operation with 05Ah (WDTPW) in the upper byte:

; Periodically clear an active watchdog

MOV #WDTPW+WDTCNTCL,&WDTCTL

;

; Change watchdog timer+ interval

MOV #WDTPW+WDTCNTL+WDTSSEL,&WDTCTL

;

; Stop the watchdog

MOV #WDTPW+WDTHOLD,&WDTCTL

;

; Change WDT+ to interval timer mode, clock/8192 interval

MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS0,&WDTCTL

345

SLAU144J–December 2004–Revised July 2013 Watchdog Timer+ (WDT+)

Submit Documentation Feedback