Datasheet

Watchdog Timer+ Operation www.ti.com
10.2 Watchdog Timer+ Operation
The WDT+ module can be configured as either a watchdog or interval timer with the WDTCTL register.
The WDTCTL register also contains control bits to configure the RST/NMI pin. WDTCTL is a 16-bit,
password-protected, read/write register. Any read or write access must use word instructions and write
accesses must include the write password 05Ah in the upper byte. Any write to WDTCTL with any value
other than 05Ah in the upper byte is a security key violation and triggers a PUC system reset regardless of
timer mode. Any read of WDTCTL reads 069h in the upper byte. The WDT+ counter clock should be
slower or equal than the system (MCLK) frequency.
10.2.1 Watchdog Timer+ Counter
The watchdog timer+ counter (WDTCNT) is a 16-bit up-counter that is not directly accessible by software.
The WDTCNT is controlled and time intervals selected through the watchdog timer+ control register
WDTCTL.
The WDTCNT can be sourced from ACLK or SMCLK. The clock source is selected with the WDTSSEL
bit.
10.2.2 Watchdog Mode
After a PUC condition, the WDT+ module is configured in the watchdog mode with an initial 32768 cycle
reset interval using the DCOCLK. The user must setup, halt, or clear the WDT+ prior to the expiration of
the initial reset interval or another PUC will be generated. When the WDT+ is configured to operate in
watchdog mode, either writing to WDTCTL with an incorrect password, or expiration of the selected time
interval triggers a PUC. A PUC resets the WDT+ to its default condition and configures the RST/NMI pin
to reset mode.
10.2.3 Interval Timer Mode
Setting the WDTTMSEL bit to 1 selects the interval timer mode. This mode can be used to provide
periodic interrupts. In interval timer mode, the WDTIFG flag is set at the expiration of the selected time
interval. A PUC is not generated in interval timer mode at expiration of the selected timer interval and the
WDTIFG enable bit WDTIE remains unchanged.
When the WDTIE bit and the GIE bit are set, the WDTIFG flag requests an interrupt. The WDTIFG
interrupt flag is automatically reset when its interrupt request is serviced, or may be reset by software. The
interrupt vector address in interval timer mode is different from that in watchdog mode.
NOTE: Modifying the Watchdog Timer+
The WDT+ interval should be changed together with WDTCNTCL = 1 in a single instruction
to avoid an unexpected immediate PUC or interrupt.
The WDT+ should be halted before changing the clock source to avoid a possible incorrect
interval.
10.2.4 Watchdog Timer+ Interrupts
The WDT+ uses two bits in the SFRs for interrupt control.
• The WDT+ interrupt flag, WDTIFG, located in IFG1.0
• The WDT+ interrupt enable, WDTIE, located in IE1.0
When using the WDT+ in the watchdog mode, the WDTIFG flag sources a reset vector interrupt. The
WDTIFG can be used by the reset interrupt service routine to determine if the watchdog caused the
device to reset. If the flag is set, then the watchdog timer+ initiated the reset condition either by timing out
or by a security key violation. If WDTIFG is cleared, the reset was caused by a different source.
When using the WDT+ in interval timer mode, the WDTIFG flag is set after the selected time interval and
requests a WDT+ interval timer interrupt if the WDTIE and the GIE bits are set. The interval timer interrupt
vector is different from the reset vector used in watchdog mode. In interval timer mode, the WDTIFG flag
is reset automatically when the interrupt is serviced, or can be reset with software.
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Watchdog Timer+ (WDT+) SLAU144J–December 2004–Revised July 2013
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