Datasheet

WDTQn
Y
0
1
2
3
Q6
Q9
Q13
Q15
16−bit
Counter
CLK
A
B
1
1
A EN
PUC
SMCLK
ACLK
Clear
Password
Compare
0
0
0
0
1
1
1
1
WDTCNTCL
WDTTMSEL
WDTNMI
WDTNMIES
WDTIS1
WDTSSEL
WDTIS0
WDTHOLD
EQU
EQU
Write Enable
Low Byte
R / W
MDB
LSB
MSB
WDTCTL
(Asyn)
Int.
Flag
Pulse
Generator
SMCLK Active
MCLK Active
ACLK Active
16−bit
Fail-Safe
Logic
Clock
Request
Logic
MCLK
www.ti.com Watchdog Timer+ (WDT+) Introduction
Figure 10-1. Watchdog Timer+ Block Diagram
343
SLAU144J–December 2004–Revised July 2013 Watchdog Timer+ (WDT+)
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