Datasheet

Interrupts
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2.2.1.4 Example of an NMI Interrupt Handler
The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE
and ACCVIE interrupt-enable bits. The user NMI service routine resets the interrupt flags and re-enables
the interrupt-enable bits according to the application needs as shown in Figure 2-5.
Figure 2-5. NMI Interrupt Handler
NOTE: Enabling NMI Interrupts with ACCVIE, NMIIE, and OFIE
To prevent nested NMI interrupts, the ACCVIE, NMIIE, and OFIE enable bits should not be
set inside of an NMI interrupt service routine.
2.2.2 Maskable Interrupts
Maskable interrupts are caused by peripherals with interrupt capability including the watchdog timer
overflow in interval-timer mode. Each maskable interrupt source can be disabled individually by an
interrupt enable bit, or all maskable interrupts can be disabled by the general interrupt enable (GIE) bit in
the status register (SR).
Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this
manual.
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System Resets, Interrupts, and Operating Modes SLAU144JDecember 2004Revised July 2013
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