Datasheet

www.ti.com SVS Operation
9.2 SVS Operation
The SVS detects if the AV
CC
voltage drops below a selectable level. It can be configured to provide a POR
or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve
current consumption.
9.2.1 Configuring the SVS
The VLDx bits are used to enable/disable the SVS and select one of 14 threshold levels (V
(SVS_IT-)
) for
comparison with AV
CC
. The SVS is off when VLDx = 0 and on when VLDx > 0. The SVSON bit does not
turn on the SVS. Instead, it reflects the on/off state of the SVS and can be used to determine when the
SVS is on.
When VLDx = 1111, the external SVSIN channel is selected. The voltage on SVSIN is compared to an
internal level of approximately 1.25 V.
9.2.2 SVS Comparator Operation
A low-voltage condition exists when AV
CC
drops below the selected threshold or when the external voltage
drops below its 1.25-V threshold. Any low-voltage condition sets the SVSFG bit.
The PORON bit enables or disables the device-reset function of the SVS. If PORON = 1, a POR is
generated when SVSFG is set. If PORON = 0, a low-voltage condition sets SVSFG, but does not generate
a POR.
The SVSFG bit is latched. This allows user software to determine if a low-voltage condition occurred
previously. The SVSFG bit must be reset by user software. If the low-voltage condition is still present
when SVSFG is reset, it will be immediately set again by the SVS.
9.2.3 Changing the VLDx Bits
When the VLDx bits are changed from zero to any non-zero value there is a automatic settling delay
t
d(SVSon)
implemented that allows the SVS circuitry to settle. The t
d(SVSon)
delay is approximately 50 µs.
During this delay, the SVS will not flag a low-voltage condition or reset the device, and the SVSON bit is
cleared. Software can test the SVSON bit to determine when the delay has elapsed and the SVS is
monitoring the voltage properly. Writing to SVSCTL while SVSON = 0 will abort the SVS automatic settling
delay, t
d(SVSon)
, and switch the SVS to active mode immediately. In doing so, the SVS circuitry might not be
settled, resulting in unpredictable behavior.
When the VLDx bits are changed from any non-zero value to any other non-zero value the circuitry
requires the time t
settle
to settle. The settling time t
settle
is a maximum of ~12 µs. See the device-specific
data sheet. There is no automatic delay implemented that prevents SVSFG to be set or to prevent a reset
of the device. The recommended flow to switch between levels is shown in the following code.
; Enable SVS for the first time:
MOV.B #080h,&SVSCTL ; Level 2.8V, do not cause POR
; ...
; Change SVS level
MOV.B #000h,&SVSCTL ; Temporarily disable SVS
MOV.B #018h,&SVSCTL ; Level 1.9V, cause POR
; ...
337
SLAU144J–December 2004–Revised July 2013 Supply Voltage Supervisor (SVS)
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