Datasheet

C
LOAD
− External Capacitance − pF
Fosc − Typical Oscillation Frequency − MHz− T
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
10 50 100
V
CC
= 3.0 V
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Figure 8-2. Typical Pin-Oscillation Frequency
8.2.7 P1 and P2 Interrupts
Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES
registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt
vector. The PxIFG register can be tested to determine the source of a P1 or P2 interrupt.
8.2.7.1 Interrupt Flag Registers P1IFG, P2IFG
Each PxIFGx bit is the interrupt flag for its corresponding I/O pin and is set when the selected input signal
edge occurs at the pin. All PxIFGx interrupt flags request an interrupt when their corresponding PxIE bit
and the GIE bit are set. Each PxIFG flag must be reset with software. Software can also set each PxIFG
flag, providing a way to generate a software initiated interrupt.
Bit = 0: No interrupt is pending
Bit = 1: An interrupt is pending
Only transitions, not static levels, cause interrupts. If any PxIFGx flag becomes set during a Px interrupt
service routine, or is set after the RETI instruction of a Px interrupt service routine is executed, the set
PxIFGx flag generates another interrupt. This ensures that each transition is acknowledged.
NOTE: PxIFG Flags When Changing PxOUT or PxDIR
Writing to P1OUT, P1DIR, P2OUT, or P2DIR can result in setting the corresponding P1IFG
or P2IFG flags.
8.2.7.2 Interrupt Edge Select Registers P1IES, P2IES
Each PxIES bit selects the interrupt edge for the corresponding I/O pin.
Bit = 0: The PxIFGx flag is set with a low-to-high transition
Bit = 1: The PxIFGx flag is set with a high-to-low transition
331
SLAU144J–December 2004–Revised July 2013 Digital I/O
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