Datasheet

Flash Memory Registers

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7.4.4 FCTL4, Flash Memory Control Register

This register is not available in all devices. See the device-specific data sheet for details.

15 14 13 12 11 10 9 8

FWKEYx, Read as 096h

Must be written as 0A5h

7 6 5 4 3 2 1 0

MRG1 MRG0

r-0 r-0 rw-0 rw-0 r-0 r-0 r-0 r-0

FWKEYx Bits 15-8 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC.

Reserved Bits 7-6 Reserved. Always read as 0.

MRG1 Bit 5 Marginal read 1 mode. This bit enables the marginal 1 read mode. The marginal read 1 bit is cleared if the

CPU starts execution from the flash memory. If both MRG1 and MRG0 are set MRG1 is active and MRG0 is

ignored.

0 Marginal 1 read mode is disabled.

1 Marginal 1 read mode is enabled.

MRG0 Bit 4 Marginal read 0 mode. This bit enables the marginal 0 read mode. The marginal mode 0 is cleared if the CPU

starts execution from the flash memory. If both MRG1 and MRG0 are set MRG1 is active and MRG0 is

ignored.

0 Marginal 0 read mode is disabled.

1 Marginal 0 read mode is enabled.

Reserved Bits 3-0 Reserved. Always read as 0.

7.4.5 IE1, Interrupt Enable Register 1

7 6 5 4 3 2 1 0

ACCVIE

rw-0

Bits 7-6 These bits may be used by other modules. See the device-specific data sheet.

ACCVIE Bit 5 Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in

IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B

instructions, rather than MOV.B or CLR.B instructions.

0 Interrupt not enabled

1 Interrupt enabled

Bits 4-0 These bits may be used by other modules. See the device-specific data sheet.

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Flash Memory Controller SLAU144J–December 2004–Revised July 2013

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