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Flash Memory Registers
7.4.3 FCTL3, Flash Memory Control Register
15 14 13 12 11 10 9 8
FWKEYx, Read as 096h
Must be written as 0A5h
7 6 5 4 3 2 1 0
FAIL LOCKA EMEX LOCK WAIT ACCVIFG KEYV BUSY
r(w)-0 r(w)-1 rw-0 rw-1 r-1 rw-0 rw-(0) r(w)-0
FWKEYx Bits 15-8 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC.
FAIL Bit 7 Operation failure. This bit is set if the fFTG clock source fails, or a flash operation is aborted from an interrupt
when EEIEX = 1. FAIL must be reset with software.
0 No failure
1 Failure
LOCKA Bit 6 SegmentA and Info lock. Write a 1 to this bit to change its state. Writing 0 has no effect.
0 Segment A unlocked and all information memory is erased during a mass erase.
1 Segment A locked and all information memory is protected from erasure during a mass erase.
EMEX Bit 5 Emergency exit
0 No emergency exit
1 Emergency exit
LOCK Bit 4 Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit can be set any time during a
byte or word write or erase operation, and the operation completes normally. In the block write mode if the
LOCK bit is set while BLKWRT = WAIT = 1, then BLKWRT and WAIT are reset and the mode ends normally.
0 Unlocked
1 Locked
WAIT Bit 3 Wait. Indicates the flash memory is being written to.
0 The flash memory is not ready for the next byte/word write
1 The flash memory is ready for the next byte/word write
ACCVIFG Bit 2 Access violation interrupt flag
0 No interrupt pending
1 Interrupt pending
KEYV Bit 1 Flash security key violation. This bit indicates an incorrect FCTLx password was written to any flash control
register and generates a PUC when set. KEYV must be reset with software.
0 FCTLx password was written correctly
1 FCTLx password was written incorrectly
BUSY Bit 0 Busy. This bit indicates the status of the flash timing generator.
0 Not Busy
1 Busy
325
SLAU144J–December 2004–Revised July 2013 Flash Memory Controller
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